723612L20PFGI中文资料瑞萨数据手册PDF规格书

• Free-running CLKA and CLKB can be asynchronous or

coincident (simultaneous reading and writing of data on a

single clock edge is permitted)

• Two independent clocked FIFOs (64 x 36 storage capacity

each) buffering data in opposite directions

• Mailbox bypass Register for each FIFO

• Programmable Almost-Full and Almost-Empty Flags

• Microprocessor interface control logic

• EFA, FFA, AEA, and AFA flags synchronized by CLKA

• EFB, FFB, AEB, and AFB flags synchronized by CLKB

• Passive parity checking on each port

• Parity generation can be selected for each port