Low Power Hex D-Type Flip-Flop

General Description The 100351 contains six D-type edge-triggered, master/slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and C

文件：94.1 Kbytes 页数：9 Pages

Fairchild

仙童半导体

Low Power Hex D-Type Flip-Flop

General Description The 100351 contains six D-type edge-triggered, master/slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and C

文件：94.1 Kbytes 页数：9 Pages

Fairchild

仙童半导体

Low Power 8-Bit Buffer with Cut-Off Drivers

General Description The 100352 contains an 8-bit buffer, individual inputs (Dn), outputs (Qn), and a data output enable pin (OEN). A Q output follows its D input when the OEN pin is LOW. A HIGH on OEN holds the outputs in a cut-off state. The cut-off state is designed to be more negative than a

文件：71.24 Kbytes 页数：8 Pages

Fairchild

仙童半导体

Low Power 8-Bit Buffer with Cut-Off Drivers

General Description The 100352 contains an 8-bit buffer, individual inputs (Dn), outputs (Qn), and a data output enable pin (OEN). A Q output follows its D input when the OEN pin is LOW. A HIGH on OEN holds the outputs in a cut-off state. The cut-off state is designed to be more negative than a

文件：71.24 Kbytes 页数：8 Pages

Fairchild

仙童半导体

Low Power 8-Bit Buffer with Cut-Off Drivers

General Description The 100352 contains an 8-bit buffer, individual inputs (Dn), outputs (Qn), and a data output enable pin (OEN). A Q output follows its D input when the OEN pin is LOW. A HIGH on OEN holds the outputs in a cut-off state. The cut-off state is designed to be more negative than a

文件：71.24 Kbytes 页数：8 Pages

Fairchild

仙童半导体

Low Power 8-Bit Buffer with Cut-Off Drivers

General Description The 100352 contains an 8-bit buffer, individual inputs (Dn), outputs (Qn), and a data output enable pin (OEN). A Q output follows its D input when the OEN pin is LOW. A HIGH on OEN holds the outputs in a cut-off state. The cut-off state is designed to be more negative than a

文件：71.24 Kbytes 页数：8 Pages

Fairchild

仙童半导体

Low Power 8-Bit Register

General Description The 100353 contains eight D-type edge triggered, master/slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN in

文件：77.27 Kbytes 页数：8 Pages

Fairchild

仙童半导体

Inductive Sensor

Features ■Threaded barrel, M8 x 1 ■Stainless steel, 1.4427 SO ■DC 2-wire, nom. 8.2 VDC ■Output acc. to DIN EN 60947-5-6 (NAMUR) ■M8 x 1 male connector ■ATEX category II 1 G, Ex zone 0 ■ATEX category II 1 D, Ex zone 20 ■SIL2 (Low Demand Mode) acc. to IEC 61508, PL c acc. to ISO 13849-1 wit

文件：386.41 Kbytes 页数：4 Pages

TURCKTurck, Inc.

图尔克德国图尔克集团公司

Low Power 8-Bit Register

General Description The 100353 contains eight D-type edge triggered, master/slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN in

文件：77.27 Kbytes 页数：8 Pages

Fairchild

仙童半导体

Low Power 8-Bit Register

General Description The 100353 contains eight D-type edge triggered, master/slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN in

文件：77.27 Kbytes 页数：8 Pages

Fairchild

仙童半导体