W634GG6MB中文资料双倍数据传输速率同步动态随机存取内存-3rd generation(第三代)数据手册Winbond规格书

描述 Description

The W634GG6MB is a 4G bits DDR3 SDRAM and speed involving -09, 09I, 09J, -11, 11I, 11J, -12, 12I, 12J, -15, 15I and 15J

特性 Features

Double Data Rate architecture: two data transfers per clock cycle
• 8 bit prefetch architecture
• Burst Length 8(BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On-The-Fly (OTF)
• Bi-directional, differential data strobes (DQS and /DQS# ) are transmitted / received with data
• DLL aligns DQ and DQS transitions with clock
• Commands entered on each positive CK edge, data and data mask are referenced to both edges of a differential data strobe pair (double data rate)
• Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
• Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)
• Data masks (DM) for write data
• Write Latency WL = AL + CWL
• System level timing calibration support via write leveling and MPR read pattern
• Asynchronous RESET# pin for Power-up initialization sequence and reset function
• Dynamic ODT mode for improved signal integrity and preselectable termination impedances during writes
• Interface: SSTL_15