UJA1069TW中文资料LIN fail-safe system basis chip数据手册恩XP规格书

描述 Description

The UJA1069 fail-safe System Basis Chip (SBC) replaces basic discrete components which are common in every Electronic Control Unit (ECU) with a Local Interconnect Network (LIN) interface. The fail-safe SBC supports all networking applications which control various power and sensor peripherals by using LIN as a local sub-bus. The fail-safe SBC contains the following integrated devices:
LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3
Advanced independent watchdog
Dedicated voltage regulator for microcontroller
Serial peripheral interface (full duplex)
Local wake-up input port
Inhibit/limp-home output port
In addition to the advantages of integrating these common ECU functions in a single package, the fail-safe SBC offers an intelligent combination of system-specific functions such as:
Advanced low-power concept
Safe and controlled system start-up behavior
Advanced fail-safe system behavior that prevents any conceivable deadlock
Detailed status reporting on system and sub-system levels
The UJA1069 is designed to be used in combination with a microcontroller and a LIN controller. The fail-safe SBC ensures that the microcontroller is always started up in a defined manner. In failure situations the fail-safe SBC will maintain the microcontroller function for as long as possible, to provide full monitoring and software driven fall-back operation.
The UJA1069 is designed for 14 V single power supply architectures and for 14 V and 42 V dual power supply architectures.

特性 Features

General
Contains a full set of LIN ECU functions: LIN transceiver
Voltage regulator for the microcontroller (5.0 V)
Enhanced window watchdog with on-chip oscillator
Serial Peripheral Interface (SPI) for the microcontroller
ECU power management system
Fully integrated autonomous fail-safe system
Designed for automotive applications: Supports 14 V and 42 V architectures
Excellent ElectroMagnetic Compatibility (EMC) performance
+-8 kV ElectroStatic Discharge (ESD) protection Human Body Model (HBM) for off-board pins
+-4 kV ElectroStatic Discharge (ESD) protection IEC 61000-4-2 for off-board pins
+-60 V short-circuit proof LIN-bus pin
Battery and LIN-bus pins are protected against transients in accordance with ISO 7637-3
Very low sleep current
Supports remote flash programming via the LIN-bus
Available in: Small 6.4 mm x 7.8 mm HTSSOP24 package with low thermal resistance
Small 8 mm x 11 mm HTSSOP32 package with low thermal resistance
LIN transceiver
LIN 2.0 and SAE J2602 compliant LIN transceiver
Enhanced error signalling and reporting
Downward compatible with LIN 1.3 and the TJA1020
Power management
Smart operating modes and power management modes
Cyclic wake-up capability in Standby and Sleep mode
Local wake-up input with cyclic supply feature
Remote wake-up capability via the LIN-bus
External voltage regulators can easily be incorporated in the power supply system (flexible and fail-safe)
42 V battery related high-side switch for driving external loads such as relays and wake-up switches
Intelligent maskable interrupt output
Fail-safe features
Safe and predictable behavior under all conditions
Programmable fail-safe coded window and time-out watchdog with on-chip oscillator, guaranteeing autonomous fail-safe system supervision
Fail-safe coded 16-bit SPI interface for the microcontroller
Global enable pin for the control of safety-critical hardware
Detection and detailed reporting of failures: On-chip oscillator failure and watchdog alerts
Battery and voltage regulator undervoltages
LIN-bus failures (short-circuits)
TXDL and RXDL clamping situations and short-circuits
Clamped or open reset line
SPI message errors
Overtemperature warning
Rigorous error handling based on diagnostics
Supply failure early warning allows critical data to be stored
23 bits of access-protected RAM is available e.g. for logging of cyclic problems
Reporting in a single SPI message; no assembly of multiple SPI frames needed
Limp-home output signal for activating application hardware in case system enters Fail-safe mode (e.g. for switching on warning lights)
Fail-safe coded activation of Software development mode and Flash mode
Unique SPI readable device type identification
Software-initiated system reset