TPS53626中文资料适用于 VR13 CPU VCORE 和 DDR 存储器的两相 D-CAP+™ 降压控制器数据手册TI规格书

描述 Description

The TPS53626 device is a driverless, VR13 SVID compliant, synchronous buckcontroller.Advanced control features such as D-CAP+ architecture with overlapping pulse support undershoot reduction (USR) and overshoot reduction(OSR) provide fasttransient response, lowest output capacitance and highefficiency. The device also supportssingle-phase operation in CCM or DCM forlight-load efficiency boost. The device integrates a fullset of VR13 I/Ofeatures including VR_READY (PGOOD), ALERT and VR_HOT.The SVID interface address allows programming from 00h to 07h.Adjustablecontrol of VOUT slew rate can be programmed as high as20mV/uS. Paired with the TI NexFET Power Stage, this totalsolution deliversexceptionally high speed and low switching loss. The TPS53626 also offers four default modes that configure VCCIO and VMCP settings with one single externalresistor to savecomponent count and board space. The TPS53626 device package is a space saving, thermally enhanced 32-pin VQFNpackagethat operates from –40°C to 105°C. For all availablepackages, see the orderable addendum at the end of the document.

特性 Features

• Intel VR13 Serial VID (SVID) Compliant
• Default Configuration Mode for VR13 VCCIO and VMCP
• 8-Bit DAC with 5-mV Step
• Optimized Efficiency at Light and Heavy Loads
• Driverless Configuration for Efficient High-Frequency Switching
• Accurate, Adjustable Voltage Positioning
• Patented AutoBalance Phase Balancing
• Programmable Auto DCM and CCM Operation
• 4.5-V to 28-V Conversion Voltage Range
• Small, 4 mm × 4 mm, 32-Pin, VQFN PowerPad Package