TMS320VC5441中文资料数字信号处理器数据手册TI规格书

描述 Description

The TMS320VC5441 fixed-point digital signal processor is a quad-core solution running at 532-MIPS performance. The 5441 consists of four DSP subsystems with shared program memory. Each subsystem consists of one TMS320C54x™ DSP core, 32K-word program/data DARAM, 64K-word data DARAM, three multichannel buffered serial ports, DMA logic, one watchdog timer, one general-purpose timer, and other miscellaneous circuitry.
The 5441 also contains a host-port interface (HPI) that allows the 5441 to be viewed as a memory-mapped peripheral to a host processor.
Each subsystem has its separate program and data spaces, allowing simultaneous accesses to program instructions and data. Two read operations and one write operation can be performed in one cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. Furthermore, data can be transferred between program and data spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The 5441 includes the control mechanisms to manage interrupts, repeated operations, and function calls. In addition, the 5441 has a total of 256K words of shared program memory (128K words shared by subsystems A and B, and another 128K words shared by subsystems C and D).
The 5441 is intended as a high-performance, low-cost, high-density DSP for remote data access or voice-over IP subsystems. It is designed to maintain the current modem architecture with minimal hardware and software impacts, thus maximizing reuse of existing modem technologies and development efforts.
The 5441 is offered in two temperature ranges and individual part numbers are shown below. (Please note that the industrial temperature device part numbers do not follow the typical numbering tradition.)
Commercial temperature devices (0°C to 85°C)        TMS320VC5441PGF532 (176-pin LQFP)        TMS320VC5441GGU532 (169-ball BGA)
Industrial temperature range devices (–40°C to 100°C)        TMS320VC5441APGF532 (176-pin LQFP)        TMS320VC5441AGGU532 (169-ball BGA)

特性 Features

• 532-MIPS Quad-Core DSP Consisting of Four Independent Subsystems
• 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel-Shifter and Two 40-Bit Accumulators Per Core
• Each Core has a Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
• Each Core has Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
• Single-Instruction Repeat and Block-Repeat Operations
• Instructions With 2 or 3 Operand Reads
• Arithmetic Instructions With Parallel Store and Parallel Load
• Output Control of CLKOUT
• Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions
• 7.5-ns Single-Cycle Fixed-Point Instruction
• Twelve Multichannel Buffered Serial Ports (McBSPs), Each With 128-Channel Selection Capability (Three McBSPs per Subsystem)
• Software-Programmable Phase-Locked Loop (PLL) Provides Several Clocking Options (Requires External TTL Oscillator)
• Four Software-Programmable Timers (One Per Subsystem)
• Sixteen General-Purpose I/Os (Four Per Subsystem)
• Provided in 169-ball MicroStar BGA™ Package (GGU Suffix)
MicroStar BGA is a trademark of Texas Instruments. IEEE Standard 1149.1-1990, Standard Test-Access Port and Boundary Scan Architecture. NOTE: This data sheet is designed to be used in conjunction with theTMS320C5000 DSP Family Functional Overview (literature number SPRU307). NOTE: Leading \"x\" in signal names identifies the subsystem; x = A, B, C, or D for subsystem A, B, C, or D, respectively. Trailing \"n\" in signal names identifies the McBSP; n = 0, 1, or 2 for McBSP0, McBSP1, or McBSP2, respectively.