TMS320DM6443数据手册集成电路（IC）的DSP（数字信号处理器）规格书PDF

描述 Description

The TMS320DM6443 (also referenced as DM6443) leverages TI's Davinci™technology to meet the networked media encode and decode application processingneeds of next-generation embedded devices. The DM6443 enables OEMs and ODMs to quickly bring to market devices featuringrobust operating systems support, rich user interfaces, high processingperformance, and long battery life through the maximum flexibility of a fullyintegrated mixed processor solution. The dual-core architecture of the DM6443 provides benefits of both DSP andReduced Instruction Set Computer (RISC) technologies, incorporating ahigh-performance TMS320C64x+™ DSP core and an ARM926EJ-S MPU core. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bitinstructions and processes 32-bit, 16-bit, or 8-bit data. The core usespipelining so that all parts of the processor and memory system can operatecontinuously. The ARM core incorporates:A coprocessor 15 (CP15) and protection module Data and program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generationin the TMS320C6000™ DSP platform. It is based on an enhanced version of thesecond-generation high-performance, advanced very-long-instruction-word (VLIW)architecture developed by Texas Instruments (TI), making these DSP cores anexcellent choice for digital media applications. The C64x is a code-compatiblemember of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of theC64x+ DSP with added functionality and an expanded instruction set. Any reference to the C64x DSP or C64x CPU also applies, unless otherwisenoted, to the C64x+ DSP and C64x+ CPU, respectively. With performance of up to 4752 million instructions per second (MIPS) at aclock rate of 594 MHz, the C64x+ core offers solutions to high-performance DSPprogramming challenges. The DSP core possesses the operational flexibility ofhigh-speed controllers and the numerical capability of array processors. TheC64x+ DSP core processor has 64 general-purpose registers of 32-bit word lengthand eight highly independent functional units&151;two multipliers for a 32-bitresult and six arithmetic logic units (ALUs). The eight functional units includeinstructions to accelerate the performance in video and imaging applications.The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for atotal of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle fora total of 4752 MMACS. For more details on the C64x+ DSP, see theTMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide(literature number SPRU732). The DM6443 also has application-specific hardware logic, on-chip memory, andadditional on-chip peripherals similar to the other C6000 DSP platform devices.The DM6443 core uses a two-level cache-based architecture. The Level 1 programcache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D)is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2)consists of an 512K-bit memory space that is shared between program and dataspace. L2 memory can be configured as mapped memory, cache, or combinations ofthe two. The peripheral set includes: 1 configurable video port; a 10/100 Mb/sEthernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; aninter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 264-bit general-purpose timers each configurable as 2 independent 32-bit timers;1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO)with programmable interrupt/event generation modes, multiplexed with otherperipherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse widthmodulator (PWM) peripherals; and 2 external memory interfaces: an asynchronousexternal memory interface (EMIFA) for slower memories/peripherals, and a higherspeed synchronous memory interface for DDR2. The DM6443 includes a Video Processing Sub-System (VPSS) that has aconfigurable Resizer and Video Processing Back-End (VPBE) output used fordisplay. The Resizer accepts image data for separate horizontal and vertical resizingfrom 1/4x to 4x in increments of 256/N, where N is between 64 and 1024. The Video Processing Back-End (VPBE) is comprised of an On-Screen DisplayEngine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2separate video windows and 2 separate OSD windows. Other configurations include2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels ofalpha blending. The VENC provides four analog DACs that run at 54 MHz, providinga means for composite NTSC/PAL video, S-Video, and/or Component video output.The VENC also provides up to 24 bits of digital output to interface to RGB888devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601with separate horizontal and vertical syncs. The Ethernet Media Access Controller (EMAC) provides an efficient interfacebetween the DM644X MPU core processor and the network. The DM6443 EMAC supportboth 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in eitherhalf- or full-duplex mode, with hardware flow control and quality of service(QOS) support. The Management Data Input/Output (MDIO) module continuously polls all 32 MDIOaddresses in order to enumerate all PHY devices in the system. Once a PHYcandidate has been selected by the MPU, the DIO module transparently monitorsits link state by reading the PHY status register. Link change events are storedin the MDIO module and can optionally interrupt the MPU, allowing the MPU topoll the link status of the device without continuously performing costly MDIOaccesses. The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6443 to easily controlperipheral devices and/or communicate with host processors. The DM6443 alsoprovides multimedia card support, MMC/SD, with SDIO support. The rich peripheral set provides the ability to control external peripheraldevices and communicate with external processors. For details on each of theperipherals, see the related sections later in this document and the associatedperipheral reference guides. The DM6443 has a complete set of development tools for both the ARM and DSP.These include C compilers, a DSP assembly optimizer to simplify programming andscheduling, and a Windows™ debugger interface for visibility into source code

特性 Features

• Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
• High-Performance Digital Media SoC
• 594-MHz C64x+™ Clock Rate
• 297-MHz ARM926EJ-S™ Clock Rate
• Eight 32-Bit C64x+ Instructions/Cycle
• 4752 C64x+ MIPS
• Fully Software-Compatible With C64x /ARM9™

• Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
• Eight Highly Independent Functional Units
• Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
• Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle

• Load-Store Architecture With Non-Aligned Support
• 64 32-Bit General-Purpose Registers
• Instruction Packing Reduces Code Size
• All Instructions Conditional
• Additional C64x+™ Enhancements
• Protected Mode Operation
• Exceptions Support for Error Detection and Program Redirection
• Hardware Support for Modulo Loop Operation


• C64x+ Instruction Set Features
• Byte-Addressable (8-/16-/32-/64-Bit Data)
• 8-Bit Overflow Protection
• Bit-Field Extract, Set, Clear
• Normalization, Saturation, Bit-Counting
• Compact 16-Bit Instructions
• Additional Instructions to Support Complex Multiplies

• C64x+ L1/L2 Memory Architecture
• 32K-Byte L1P Program RAM/Cache (Direct Mapped)
• 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
• 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)

• ARM926EJ-S (MPU) Core
• Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
• DSP Instruction Extensions and Single Cycle MAC
• ARM® Jazelle® Technology
• EmbeddedICE-RT™ Logic for Real-Time Debug

• ARM9 Memory Architecture
• 16K-Byte Instruction Cache
• 8K-Byte Data Cache
• 16K-Byte RAM
• 16K-Byte ROM

• Emulation Trace Buffer™ (ETB11™) With 4-KB Memory for ARM9 Debug
• Endianness: Little Endian for ARM and DSP
• Video Processing Subsystem
• Resize Engine Provides:
• Resize Images From 1/4x to 4x
• Separate Horizontal and Vertical Control

• Back End Provides:
• Hardware On-Screen Display (OSD)
• 4 - 54 MHz DACs for a Combination of
• Composite NTSC/PAL Video
• Luma/Chroma Separate Video (S-video)
• Component (YPbPr or RGB) Video (Progressive)

• Digital Output
• 8-/16-Bit YUV or up to 24-Bit RGB
• HD Resolution
• Up to 2 Video Windows



• External Memory Interfaces (EMIFs)
• 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8V I/O)
• Asynchronous16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach
• Flash Memory Interfaces
• NOR (8-/16-Bit-Wide Data)
• NAND (8-/16-Bit-Wide Data)



• Flash Card Interfaces
• Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
• CompactFlash Controller With True IDE Mode
• SmartMedia

• Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels)
• Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
• One 64-Bit Watch Dog Timer
• Three UARTs (One with RTS and CTS Flow Control)
• One Serial Port Interface (SPI) with Two Chip-Selects
• Master/Slave Inter-Integrated Circuit (I2C Bus™)
• Audio Serial Port (ASP)
• I2S
• AC97 Audio Codec Interface
• Standard Voice Codec Interface (AIC12)

• 10/100 Mb/s Ethernet MAC (EMAC)
• IEEE 802.3 Compliant
• Media Independent Interface (MII)

• VLYNQ™ Interface (FPGA Interface)
• Host-Port Interface (HPI) with 16-Bit Multiplexed Address/Data
• USB Port With Integrated 2.0 PHY
• USB 2.0 High-/Full-Speed (480 Mbps) Client
• USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device)

• Three Pulse Width Modulator (PWM) Outputs
• On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART
• ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
• Individual Power-Saving Modes for ARM/DSP
• Flexible PLL Clock Generators
• IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
• Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
• 361-Pin Pb-Free BGA Package (ZWT Suffix), 0.8-mm Ball Pitch
• 0.09-µm/6-Level Cu Metal Process (CMOS)
• 3.3-V and 1.8-V I/O, 1.2-V Internal
• Applications:
• Digital Media
• Networked Media Encode/Decode
• Video Imaging