TMS320DM6433中文资料数字媒体处理器数据手册TI规格书

描述 Description

The TMS320C64x+™ DSPs (including the TMS320DM6433 device) are thehighest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform.The DM6433 device is based on the third-generation high-performance, advancedVelociTI™ very-long-instruction-word (VLIW) architecture developed by TexasInstruments (TI), making these DSPs an excellent choice for digital mediaapplications. The C64x+™ devices are upward code-compatible from previousdevices that are part of the C6000™ DSP platform. The C64x™ DSPs support addedfunctionality and have an expanded instruction set from previous devices.
Any reference to the C64x DSP or C64x CPU also applies, unless otherwisenoted, to the C64x+ DSP and C64x+ CPU, respectively.
With performance of up to 4800 million instructions per second (MIPS) at aclock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSPprogramming challenges. The DSP core possesses the operational flexibility ofhigh-speed controllers and the numerical capability of array processors. TheC64x+ DSP core processor has 64 general-purpose registers of 32-bit word lengthand eight highly independent functional units-two multipliers for a 32-bitresult and six arithmetic logic units (ALUs). The eight functional units includeinstructions to accelerate the performance in video and imaging applications.The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for atotal of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle fora total of 4800 MMACS. For more details on the C64x+ DSP, see theTMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature numberSPRU732).
The DM6433 also has application-specific hardware logic, on-chip memory, andadditional on-chip peripherals similar to the other C6000 DSP platform devices.The DM6433 core uses a two-level cache-based architecture. The Level 1 programmemory/cache (L1P) consists of a 256K-bit memory space that can be configured asmapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a640K-bit memory space-384K-bit of which is mapped memory and 256K-bit of whichcan be configured as mapped memory or 2-way set-associative cache. The Level 2memory/cache (L2) consists of a 1M-bit memory space that is shared betweenprogram and data space. L2 memory can be configured as mapped memory, cache, orcombinations of the two.
The peripheral set includes: 1 configurable video port; a 10/100 Mb/sEthernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bittransmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Businterface; a multichannel buffered serial port (McBSP0); a multichannel audioserial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers eachconfigurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; auser-configurable 16-bit host-port interface (HPI); up to 111-pins ofgeneral-purpose input/output (GPIO) with programmable interrupt/event generationmodes, multiplexed with other peripherals; a UART with hardware handshakingsupport; 3 pulse width modulator (PWM) peripherals; 1 peripheral componentinterconnect (PCI) [33 MHz]; and 2 glueless external memory interfaces: anasynchronous external memory interface (EMIFA) for slower memories/peripherals,and a higher speed synchronous memory interface for DDR2.
The DM6433 device includes a Video Processing Subsystem (VPSS) with a VideoProcessing Back-End (VPBE) output.
The Video Processing Back-End (VPBE) is comprised of an On-Screen DisplayEngine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2separate video windows and 2 separate OSD windows. Other configurations include2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels ofalpha blending. The VENC provides four analog DACs that run at 54 MHz, providinga means for composite NTSC/PAL video, S-Video, and/or Component video output.The VENC also provides up to 24 bits of digital output to interface to RGB888devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601with separate horizontal and vertical syncs.
The Resizer accepts image data for separate horizontal and vertical resizingfrom 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.
The Ethernet Media Access Controller (EMAC) provides an efficient interfacebetween the DM6433 and the network. The DM6433 EMAC support both 10Base-T and100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- orfull-duplex mode, with hardware flow control and quality of service (QOS)support.
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIOaddresses in order to enumerate all PHY devices in the system.
The I2C and VLYNQ ports allow DM6433 to easily control peripheral devicesand/or communicate with host processors.
The rich peripheral set provides the ability to control external peripheraldevices and communicate with external processors. For details on each of theperipherals, see the related sections later in this document and the associatedperipheral reference guides.
The DM6433 has a complete set of development tools. These include Ccompilers, a DSP assembly optimizer to simplify programming and scheduling, anda Windows™ debugger interface for visibility into source code

特性 Features

• Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
• 2.5-, 2-, 1.67, 1.51-, 1.43-ns Instruction Cycle Time
• Eight 32-Bit C64x+ Instructions/Cycle
• Fully Software-Compatible With C64x
• Low-Power Device (L suffix)
• Eight Highly Independent Functional Units With VelociTI.2 Extensions:
• Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
• Load-Store Architecture With Non-Aligned Support
• Instruction Packing Reduces Code Size
• Additional C64x+™ Enhancements
• Protected Mode Operation
• Hardware Support for Modulo Loop Auto-Focus Module Operation
• Byte-Addressable (8-/16-/32-/64-Bit Data)
• Bit-Field Extract, Set, Clear
• VelociTI.2 Increased Orthogonality
• Compact 16-bit Instructions
• C64x+ L1/L2 Memory Architecture
• 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
• 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
• Video Processing Subsystem (VPSS)
• Front End Provides (Resizer Only):
• Resize Images From 1/4× to 4×
• Back End Provides:
• Hardware On-Screen Display (OSD)
• Composite NTSC/PAL Video
• Component (YPbPr or RGB) Video (Progressive)
• 8-/16-bit YUV or up to 24-Bit RGB
• Up to 2 Video Windows
• 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
• Supports up to 333-MHz (data rate) bus and interfaces to DDR2-400 SDRAM
• Flash Memory Interfaces
• NOR (8-Bit-Wide Data)
• Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
• One 64-Bit Watch Dog Timer
• Master/Slave Inter-Integrated Circuit (I2C Bus™)
• I2S and TDM
• SPI
• Telecom Interfaces - ST-Bus, H-100
• Multichannel Audio Serial Port (McASP0)
• Four Serializers and SPDIF (DIT) Mode
• 32-Bit 33-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface
• IEEE 802.3 Compliant
• Management Data I/O (MDIO) Module
• Three Pulse Width Modulator (PWM) Outputs
• Individual Power-Savings Modes
• IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
• Packages:
• 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
• 0.09-µm/6-Level Cu Metal Process (CMOS)
• 3.3-V and 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5)
• Digital Media
• Networked Media Decode All trademarks are the property of their respectiveowners.

简介

TMS320DM6433属于集成电路（IC）的DSP（数字信号处理器）。由TI制造生产的TMS320DM6433DSP（数字信号处理器）数字信号处理器是类似于微处理器或微控制器的器件，但区别在于其内部架构经修改，适用于对连续数据流连续执行以乘法和加法运算为主的算法，而不是以条件逻辑或大量并发进程为主的算法。该器件通常用于诸如音频或视频信号处理等应用。