TMS320C6747中文资料低功耗 C674x 浮点 DSP- 456MHz、PBGA数据手册TI规格书

描述 Description

The TMS320C6745/6747 device is a low-power digital signal processor based on a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The TMS320C6745/6747 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance .

The TMS320C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128KB of RAM shared memory (TMS320C6747 only) is available for use by other hosts without affecting DSP performance.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/9 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI) [TMS320C6747 only]; up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the TMS320C6745/6747 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

特性 Features

• Software Support
• Chip Support Library and DSP Library
• 375- and 456-MHz TMS320C674x VLIW DSP
• Superset of the C67x+ and C64x+ ISAs
• Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
• Bit-Field Extract, Set, Clear
• Compact 16-Bit Instructions
• C674x Two-Level Cache Memory Architecture
• 32KB of L1D Data RAM/Cache
• Flexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct Memory Access Controller 3 (EDMA3):
• 32 Independent DMA Channels
• Programmable Transfer Burst Size
• TMS320C674x Fixed- and Floating-Point VLIW DSP Core
• 64 General-Purpose Registers (32-Bit)
• Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
• Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
• Two Multiply Functional Units
• 2 SP x SP -> SP Per Clock
• 2 SP x DP -> DP Every Three Clocks
• Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
• Instruction Packing Reduces Code Size
• Hardware Support for Modulo Loop Operation
• Exceptions Support for Error Detection and Program Redirection
• 128KB of RAM Shared Memory (TMS320C6747 Only)
• Two External Memory Interfaces:
• NOR (8- or 16-Bit-Wide Data)
• 16-Bit SDRAM with 128-MB Address Space (TMS320C6747 Only)
• EMIFB
• 16-Bit SDRAM with 128-MB Address Space (TMS320C6745)
• Three Configurable 16550-Type UART Modules:
• Autoflow Control Signals (CTS, RTS) on UART0 Only
• 16x or 13x Oversampling Option
• LCD Controller (TMS320C6747 Only)
• Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
• One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth (TMS320C6747 Only)
• Two Independent Programmable Realtime Unit (PRU) Cores
• 4KB of Instruction RAM per Core
• PRUSS can be Disabled via Software to Save Power
• Standard Power-Management Mechanism
• Entire Subsystem Under a Single PSC Clock Gating Domain
• Dedicated Interrupt Controller
• USB 1.1 OHCI (Host) with Integrated PHY (USB1) (TMS320C6747 Only)
• USB 2.0 High- and Full-Speed Client (TMS320C6747)
• USB 2.0 High-, Full-, and Low-Speed Host (TMS320C6747)
• High-Speed Functionality Available on TMS320C6747 Device Only
• End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
• Three Multichannel Audio Serial Ports (McASPs):
• TMS320C6745 Supports 2 McASPs
• Supports TDM, I2S, and Similar Formats
• FIFO Buffers for Transmit and Receive
• 10/100 Mbps Ethernet MAC (EMAC):
• RMII Media-Independent Interface
• Real-Time Clock with 32-kHz Oscillator and Separate Power Rail (TMS320C6747 Only)
• One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
• Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
• Dead-Band Generation
• Trip Zone Input
• Three 32-Bit Enhanced Capture (eCAP) Modules:
• Single-Shot Capture of up to Four Event Time-Stamps
• Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
• 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
• TMS320C6745 Device:
• Commercial, Industrial, Extended, or Automotive Temperature