TMS320C6743中文资料低功耗 C674x 浮点 DSP- 375MHz数据手册TI规格书

描述 Description

The C6743 device is a low-power digital signal processor based on C674x DSP core. The device consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The C6743 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance.

The C6743 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 128-KB of memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; two multichannel audio serial ports (McASPs) with 14/9 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; two UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces (EMIFs): an asynchronous external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6743 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

特性 Features

• Applications
• High-Speed Encoding
• Software Support
• Chip Support Library and DSP Library
• 375-MHz TMS320C674x Fixed- and Floating-Point VLIW DSP Core
• 64 General-Purpose Registers (32-Bit)
• Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
• Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
• Two Multiply Functional Units
• 2 SP x SP -> SP Per Clock
• 2 SP x DP -> DP Every Three Clocks
• Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
• Instruction Packing Reduces Code Size
• Hardware Support for Modulo Loop Operation
• Exceptions Support for Error Detection and Program Redirection
• C674x Instruction Set Features
• 3000 MIPS and 2250 MFLOPS C674x
• 8-Bit Overflow Protection
• Normalization, Saturation, Bit-Counting
• C674x Two-Level Cache Memory Architecture
• 32KB of L1D Data RAM/Cache
• Flexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct Memory Access Controller 3 (EDMA3):
• 32 Independent DMA Channels
• Programmable Transfer Burst Size
• 3.3-V LVCMOS I/Os
• EMIFA
• NAND (8-Bit-Wide Data)
• EMIFB
• Two Configurable 16550-Type UART Modules:
• 16-Byte FIFO
• One Serial Peripheral Interface (SPI) with One Chip Select
• Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
• Two Independent Programmable Real-Time Unit (PRU) Cores
• 4KB of Instruction RAM per Core
• PRUSS can be Disabled Through Software to Save Power
• Standard Power-Management Mechanism
• Entire Subsystem Under a Single PSC Clock Gating Domain
• Dedicated Interrupt Controller
• Two Multichannel Audio Serial Ports (McASPs):
• FIFO Buffers for Transmit and Receive
• 10/100 Mbps RMII Ethernet Media Access Controller (EMAC):
• RMII Media-Independent Interface
• One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
• Three Enhanced Pulse Width Modulators (eHRPWMs):
• 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
• PWM Chopping by High-Frequency Carrier
• Three 32-Bit Event Capture (eCAP) Modules:
• Single-Shot Capture of up to Four Event Time-Stamps
• Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
• 176-Pin Thin Quad Flat Pack (TQFP) [PTP Suffix], 0.5-mm Pin Pitch
• Commercial or Automotive Temperature