TMS320C6713B中文资料C67x 浮点 DSP- 高达 300MHz、McBSP、16 位 EMIFA数据手册TI规格书

描述 Description

The TMS320C67x™ DSPs (including the TMS320C6713B device) compose the floating-point DSP generation in the TMS320C6000™ DSP platform. The C6713B device is based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications.

Operating at 225 MHz, the C6713B delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS).

Operating at 300 MHz, the C6713B delivers up to 1800 million floating-point operations per second (MFLOPS), 2400 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 600 million multiply-accumulate operations per second (MMACS).

The C6713B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 4K-byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-byte 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-byte memory space that is shared between program and data space. 64K bytes of the 256K bytes in L2 memory can be configured as mapped memory, cache, or combinations of the two. The remaining 192K bytes in L2 serves as mapped SRAM.

The C6713B has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals.

The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713B has sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The two I2C ports on the TMS320C6713B allow the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The TMS320C6713B device has two bootmodes: from the HPI or from external asynchronous ROM. For more detailed information, see the bootmode section of this data sheet.

The TMS320C67x DSP generation is supported by the TI eXpressDSP™ set of industry benchmark development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studio™ Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOS™ kernel.

The TMS320C67x™ DSPs (including the TMS320C6713B device) compose the floating-point DSP generation in the TMS320C6000™ DSP platform. The C6713B device is based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications.

Operating at 225 MHz, the C6713B delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS).

Operating at 300 MHz, the C6713B delivers up to 1800 million floating-point operations per second (MFLOPS), 2400 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 600 million multiply-accumulate operations per second (MMACS).

The C6713B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 4K-byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-byte 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-byte memory space that is shared between program and data space. 64K bytes of the 256K bytes in L2 memory can be configured as mapped memory, cache, or combinations of the two. The remaining 192K bytes in L2 serves as mapped SRAM.

The C6713B has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals.

The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713B has sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The two I2C ports on the TMS320C6713B allow the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The TMS320C6713B device has two bootmodes: from the HPI or from external asynchronous ROM. For more detailed information, see the bootmode section of this data sheet.

The TMS320C67x DSP generation is supported by the TI eXpressDSP™ set of industry benchmark development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studio™ Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOS™ kernel.

特性 Features

• Highest-Performance Floating-Point Digital Signal Processor (DSP): TMS320C6713B
• 32/64-Bit Data Word
• 3.3-, 4.4-, 5-, 6-Instruction Cycle Times
• Rich Peripheral Set, Optimized for Audio
• Extended Temperature Devices Available
• Advanced Very Long Instruction Word (VLIW) TMS320C67x™ DSP Core
• 2 ALUs (Fixed-Point)
• 2 Multipliers (Floating-/Fixed-Point)
• Load-Store Architecture With 32 32-Bit General-Purpose Registers
• All Instructions Conditional
• Instruction Set Features
• Single- and Double-Precision
• Byte-Addressable (8-, 16-, 32-Bit Data)
• Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization
• L1/L2 Memory Architecture
• 4K-Byte L1D Data Cache (2-Way)
• Device Configuration
• Endianness: Little Endian, Big Endian
• 32-Bit External Memory Interface (EMIF)
• 512M-Byte Total Addressable External Memory Space
• Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
• Two McASPs
• Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones
• Programmable Clock Generator
• TDM Streams From 2-32 Time Slots
• Data Formatter for Bit Manipulation
• Wide Variety of I2S and Similar Bit Stream Formats
• S/PDIF, IEC60958-1, AES-3, CP-430 Formats
• Enhanced Channel Status/User Data
• Extensive Error Checking and Recovery
• Two Inter-Integrated Circuit Bus (I2C Bus™) Multi-Master and Slave Interfaces
• Serial-Peripheral-Interface (SPI)
• AC97 Interface
• Two 32-Bit General-Purpose Timers
• Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module
• 208-Pin PowerPAD™ PQFP (PYP)
• 0.13-µm/6-Level Copper Metal Process
• 3.3-V I/Os, 1.2-V Internal (GDP/ZDP/ PYP)
• 3.3-V I/Os, 1.4-V Internal (GDP/ZDP) [300 MHz]
TMS320C67x and PowerPAD are trademarks of Texas Instruments. I2C Bus is a trademark of Philips Electronics N.V. Corporation

简介

TMS320C6713B属于集成电路（IC）的DSP（数字信号处理器）。由TI制造生产的TMS320C6713BDSP（数字信号处理器）数字信号处理器是类似于微处理器或微控制器的器件，但区别在于其内部架构经修改，适用于对连续数据流连续执行以乘法和加法运算为主的算法，而不是以条件逻辑或大量并发进程为主的算法。该器件通常用于诸如音频或视频信号处理等应用。