TMS320C6474中文资料多核数字信号处理器数据手册TI规格书

描述 Description

The TMS320C64x+ DSPs (including the TMS320C6474 device) are the highest-performance multicore DSP generation in the TMS320C6000™ DSP platform.
The C6474 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI).
The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

特性 Features

• Key Features
• Instruction Cycle Time: 0.83 ns (1.2-GHz Device); 1 ns (1-GHz Device); 1.18 ns (850-MHz Device)
• Commercial Temperature and Extended Tmperature
• Enhanced VCP2/TCP2
• 16-/32-Bit DDR2-667 Memory Controller
• Antenna Interface
• One 1.8-V Inter-Integrated Circuit (I2C) Bus
• 1000 Mbps Ethernet MAC (EMAC)
• 16 General-Purpose I/O (GPIO) Pins
• System PLL and PLL Controller/DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
• High-Performance Multicore DSP (C6474)
• 1.2-GHz Device: 1.0-ns to 0.83-ns
• 850-MHz Device: 1.18 ns
• Clock Rate:
• 1-GHz Device: 1-GHz
• Eight 32-Bit Instructions/Cycle
• 1.2-GHz Device: 0°C to 95°C
• 850-MHZ and 1-GHz Device: 0°C to 100°C
• Extended Temperature:
• 1-GHz Device: -40°C to 100°C
• 3 TMS320C64x+™ DSP Cores
• Compact Instructions (16-Bit)
• TMS320C64x+ Megamodule L1/L2 Memory Architecture
• 256 K-Bit (32 K-Byte) L1D Data Cache [2-Way Set-Associative]
• Enhanced VCP2
• Enhanced Turbo Decoder Coprocessor (TCP2)
• Endianness: Little Endian, Big Endian
• Time Alignment Between Internal Subsystems, External Devices/System
• Alternate Interfaces for non-RP1 and non-UMTS Systems
• 16-/32-Bit DDR2-667 Memory Controller
• Antenna Interface
• Supports OBSAI RP3 Protocol, v1.0: 768-Mbps, 1.536-, 3.072-Gbps Link Rates
• Clock Input Independent or Shared with CPU (Selectable at Boot-Time)
• Two 1x Serial RapidIO® Links, v1.2 Compliant
• Message Passing and DirectIO Support
• One 1.8-V Inter-Integrated Circuit (I2C) Bus
• 1000 Mbps Ethernet MAC (EMAC)
• Supports SGMII, v1.8 Compliant
• Six 64-Bit General-Purpose Timers
• Configurable in a Watchdog Timer mode
• 16 General-Purpose I/O (GPIO) Pins
• Software Method to Control Access to Shared Resources
• System PLL and PLL Controller
• IEEE-1149.1 and IEEE-1149.6 (JTAG™) Boundary-Scan-Compatible
• 0.065-µm/7-Level Cu Metal Process (CMOS)
• 1.8-V, 1.1-V I/Os
Note:Advance Information is presented in this document for the C6474 1.2-GHz extended temperature device.