TMS320C6701中文资料C67x 浮点 DSP- 高达 167MHz、McBSP数据手册TI规格书

描述 Description

The TMS320C67x DSPs are the floating-point DSP family in the TMS320C6000™ DSP platform. The TMS320C6701 (C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the C6701 offers cost-effective solutions to high-performance DSP programming challenges. The C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

特性 Features

• Highest Performance Floating-Point Digital Signal Processor (DSP) TMS320C6701
• 120-, 150-, 167-MHz Clock Rate
• 1 GFLOPS
• VelociTI™ Advanced Very Long Instruction Word (VLIW) C67x™ CPU Core
• Four ALUs (Floating- and Fixed-Point)
• Two Multipliers (Floating- and Fixed-Point)
• Load-Store Architecture With 32 32-Bit General-Purpose Registers
• All Instructions Conditional
• Instruction Set Features
• Hardware Support for IEEE Double-Precision Instructions
• 8-Bit Overflow Protection
• Bit-Field Extract, Set, Clear
• Normalization
• 1M-Bit On-Chip SRAM
• 512K-Bit Dual-Access Internal Data (64K Bytes)
• 32-Bit External Memory Interface (EMIF) to Synchronous/Asynchronous Memories
• Glueless Interface to Asynchronous Memories: SRAM and EPROM
• Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel
• Access to Entire Memory Map
• Two Multichannel Buffered Serial Ports (McBSPs)
• ST-Bus-Switching Compatible
• AC97-Compatible
• Two 32-Bit General-Purpose Timers
• IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
• 0.18-µm/5-Level Metal Process
• 3.3-V I/Os, 1.8-V Internal (120-, 150-MHz)
• 3.3-V I/Os, 1.9-V Internal (167-MHz Only)
VelociTI is a trademark of Texas Instruments. Motorola is a trademark of Motorola, Inc. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. TMS320C6000 is a trademark of Texas Instruments. Windows is a registered trademark of Microsoft Corporation.