6-BIT 2:1 MUX-REGISTER

DESCRIPTION The SY10/100E167 offer six 2:1 multiplexers followed by D flip-flops with single-ended outputs, designed for use in new, high-performance ECL systems. FEATURES ■ 1000MHz min. operating frequency ■ Extended 100E VEE range of –4.2V to –5.5V ■ 800ps max. clock to output ■ Single-en

文件：155.24 Kbytes 页数：3 Pages

MICREL

麦瑞半导体

6-BIT 2:1 MUX-REGISTER

Description The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2 (or both). A HIGH on the Master Reset (

文件：105.97 Kbytes 页数：4 Pages

ONSEMI

安森美半导体

6-BIT 2:1 MUX-REGISTER

DESCRIPTION The SY10/100E167 offer six 2:1 multiplexers followed by D flip-flops with single-ended outputs, designed for use in new, high-performance ECL systems. FEATURES ■ 1000MHz min. operating frequency ■ Extended 100E VEE range of –4.2V to –5.5V ■ 800ps max. clock to output ■ Single-en

文件：155.24 Kbytes 页数：3 Pages

MICREL

麦瑞半导体

6-BIT 2:1 MUX-REGISTER

DESCRIPTION The SY10/100E167 offer six 2:1 multiplexers followed by D flip-flops with single-ended outputs, designed for use in new, high-performance ECL systems. FEATURES ■ 1000MHz min. operating frequency ■ Extended 100E VEE range of –4.2V to –5.5V ■ 800ps max. clock to output ■ Single-en

文件：155.24 Kbytes 页数：3 Pages

MICREL

麦瑞半导体