SY10E167数据手册集成电路（IC）的信号开关多路复用器解码器规格书PDF

描述 Description

The SY10/100E167 offers six 2:1 multiplexers followed by D flip-flops with single-ended outputs, designed for use in new, high-performance ECL systems. The Select (SEL) control allows one of the two data inputs to the multiplexer to pass through. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as control for the six flip-flops. The selected data are transferred to the flip-flops on the rising edge of CLK1 or CLK2 (or both).The multiplexer operation is controlled by the Select (SEL) signal which selects one of the two bits of input data at each mux to be passed through.When a logic HIGH is applied to the Master Reset (MR) signal, it operates asychronously to take all outputs Q to a logic LOW.

特性 Features

·1000MHz min. operating frequency
·Extended 100E VEE range of –4.2V to –5.5V
·800ps max. clock to output
·Single-ended outputs
·Asynchronous Master Reset
·Dual clocks
·Fully compatible with industry standard 10KH, 100K ECL levels
·Internal 75KΩ input pulldown resistors
·ESD protection of 2000V
·Fully compatible with Motorola MC10E/100E167
·Available in 28-pin PLCC package

简介

SY10E167属于集成电路（IC）的信号开关多路复用器解码器。由制造生产的SY10E167信号开关，多路复用器，解码器逻辑型信号开关、多路复用器和编码器 IC 可用于对以数字格式表示数据的电信号进行路由和选择。这些器件与设计用于模拟信号的类似产品有所不同，它们保留的信息表示为两个电状态之一，而不是两个外部界限内的无穷变化量。