SY100E452中文资料Flip Flops, Registers Products数据手册Microchip规格书

描述 Description

The SY10/100E452 are 5-bit differential registers with differential data (inputs and outputs) and clock. The registers are triggered by a positive transition of the positive clock (CLK) input. A high on the Master Reset (MR) asynchronously resets all registers so that the Q outputs go LOW.The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the devices. The clamping action will assert the /D and the /CLK sides of the inputs.Because of the edge-triggered flip-flop nature of the devices, simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state.The fully differential design of the devices makes them ideal for very high frequency applications where a registered data path is necessary.

特性 Features

·Differential D, CLK and Q
·Extended 100E VEE range of -4.2V to -5.5V
·VBB output for single-ended use
·1100MHz min. toggle frequency
·Asynchronous Master Reset
·Fully compatible with Motorola MC10E/100E452
·Available in 28-pin PLCC package

简介

SY100E452属于集成电路（IC）的触发器。由制造生产的SY100E452触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。