SY100E196中文资料Skew Management Products数据手册Microchip规格书

描述 Description

The SY10/100E196 are programmable delay chips (PDCs) designed primarily for very accurate differential ECL input edge placement applications.The delay section consists of a chain of gates and a linear ramp delay adjustment organized as shown in the logic diagram. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80ps. These two elements provide the E196 with a digitally-selectable resolution of approximately 20ps. The required device delay is selected by the seven address inputs D[0:6], which are latched on-chip by a high signal on the latch enable (LEN) control. If the LEN signal is either LOW or left floating, then the latch is transparent.The FTUNE input takes an analog coltage and applies it to an internal linear ramp for reducing the 20s resolution still further. The FTUNE input is what differentiates the E196 from the E195.An eighth latched input, D7, is provided for cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs, at the expense of only a single added line to the data bus for each additional PDC, without the need for any external gating.

特性 Features

·Up to 2ns delay range
·Extended 100E VEE range of –4.2V to –5.5V
·≈20ps/digital step resolution
·Linear input for tighter resolution
·>1GHz bandwidth
·On-chip cascade circuitry
·75kΩ input pulldown resistor
·Fully compatible with Motorola MC10E/100E196
·Available in 28-pin PLCC package

简介

SY100E196属于集成电路（IC）的延迟线。由Microchip制造生产的SY100E196延迟线时钟延迟线产品族中的产品属于数字器件，用于在数字信号中引入时间延迟，以便将提交给器件输入的信号跃迁，经过某一已知时间之后在输出端复现。它们常用于高速数字系统，以校正或补偿不同信号路径之间的信号传播时间的偏差。这些器件可用于产生固定、可选或可变持续时间的延迟。