SY100E131中文资料Flip Flops, Registers Products数据手册Microchip规格书

描述 Description

The SY10/100E131 are high-speed quad master slave D-type flip-flops with differential outputs designed for use in new, high-performance ECL systems. The flip-flops may be individually clocked by holding CC (Common Clock) at a logic LOW and then using the four individual CE (Clock Enable CE0-CE3) inputs to accomplish such clocking. Alternatively, all four flip-flops can be clocked in common by holding the CE inputs LOW and then using CC to clock the data. In the common clock mode, the CE input acts as a control that passes the CC signal to the flip-flop. Data is clocked into the flip-flop on the rising edge of the output of the logical OR operation between CE and CC (data enters the master when both CC and CE are LOW and data transfers to the slave when either CE or CC, or both, go HIGH).Asynchronous set and reset controls are provided. The reset controls are individual and the set controls are pairwise.

特性 Features

·1100MHz min. toggle frequency
·Extended 100E VEE range of -4.2V to -5.5V
·Differential output
·Individual and common clocks
·Indivldual asynchronous reset
·Paired asynchronous sets
·Fully compatible with Industry standard 10KH, 100K ECL levels
·Internal 75KΩ input pulldown resistors
·Fully compatible with Motorola MC10E/100E131
·Available in 28-pin PLCC package

简介

SY100E131属于集成电路（IC）的触发器。由制造生产的SY100E131触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。