SY100E112JC数据手册集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF

描述 Description

DESCRIPTION
The SY10/100E112 are quad drivers designed for use in new, high-performance ECL systems. The E112 has two pairs of OR/NOR outputs from each gate and a common, buffered enable input. The data input can also be used as an ECL memory address fan-out driver, although the E111 is designed specifically for this purpose, and offers lower skew than the E112. For memory address driver applications where scan capabilities are required, please refer to the SY10/100E212 device.FEATURES
■ 600ps max. propagation delay
■ Extended 100E VEE range of –4.2V to –5.5V
■ Common enable input
■ Fully compatible with industry standard 10KH, 100K
   I/O levels
■ Internal 75KΩ input pulldown resistors
■ Fully compatible with Motorola MC10E/100E112
■ Available in 28-pin PLCC package

特性 Features

■ 600ps max. propagation delay
■ Extended 100E VEE range of –4.2V to –5.5V
■ Common enable input
■ Fully compatible with industry standard 10KH, 100K
   I/O levels
■ Internal 75KΩ input pulldown resistors
■ Fully compatible with Motorola MC10E/100E112
■ Available in 28-pin PLCC package

简介

SY100E112JC属于集成电路（IC）的缓冲器驱动器接收器收发器。由制造生产的SY100E112JC缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。