STGAP2S

STGAP2S

Features •Highvoltagerailupto1700V •Drivercurrentcapability:4Asink/source@25°C •dV/dttransientimmunity±100V/nsinfulltemperaturerange •Overallinput-outputpropagationdelay:75ns •Separatesinkandsourceoptionforeasygatedrivingconfiguration •4AMillerCLAMP

STGAP2S

电流隔离4 A单重栅极驱动器; • 1700V单通道栅极驱动器 \n• 驱动器电流能力：4 A，温度为25°C \n• dV/ dt瞬态抗扰度±100 V / ns \n• 总输入 - 输出传播延迟：80 ns \n• 独立的输出状态，便于栅极驱动配置 \n• 4A专用密勒钳位引脚• UVLO功能 \n• 栅极驱动电压高达26 V \n• 具有迟滞的3.3 V，5 V TTL / CMOS输入 \n• 温度关闭保护 \n• 待机功能;

STGAP2S是单栅极驱动器，可将栅极驱动通道与低压控制和接口电路部分隔离。\n\n 栅极驱动器具有4A电流驱动和轨到轨输出，使该器件适用于大功率逆变器应用，如工业应用中的电机驱动器。\n\n 该设备有两种不同的配置。具有独立输出引脚的配置可以使用栅极电阻独立优化导通和关断。具有单输出引脚和米勒钳位功能的配置可防止半桥拓扑中快速换向期间的栅极峰值。\n\n 两种配置均可为外部组件提供高度灵活性和减少外部材料清单。\n\n 该器件集成了保护功能：包括UVLO和热关断功能，可轻松设计高可靠性系统。双输入引脚允许选择控制信号极性并实现硬件互锁保护，避免主控制器故障时发生传导。\n\n 输入到输出的传播延迟在80 ns内，PWM控制精度高。\n\n 可以使用待机模式以降低空闲时的功耗。\n\n

STGAP2SCM

STGAP2S

Features •Highvoltagerailupto1700V •Drivercurrentcapability:4Asink/source@25°C •dV/dttransientimmunity±100V/nsinfulltemperaturerange •Overallinput-outputpropagationdelay:75ns •Separatesinkandsourceoptionforeasygatedrivingconfiguration •4AMillerCLAMP

STGAP2SCMTR

STGAP2S

Features •Highvoltagerailupto1700V •Drivercurrentcapability:4Asink/source@25°C •dV/dttransientimmunity±100V/nsinfulltemperaturerange •Overallinput-outputpropagationdelay:75ns •Separatesinkandsourceoptionforeasygatedrivingconfiguration •4AMillerCLAMP

STGAP2SICS

Galvanically isolated 4 A single gate driver for SiC MOSFETs

Features •Highvoltagerailupto1200V •Drivercurrentcapability:4Asink/source@25°C •dV/dttransientimmunity±100V/nsinfulltemperaturerange •Overallinput-outputpropagationdelay:75ns •Separatesinkandsourceoptionforeasygatedrivingconfiguration •4AMillerCLAMP

STGAP2SICS

Galvanically isolated 4 A single gate driver for SiC MOSFETs; • High voltage rail up to 1200 V \n• Driver current capability: 4 A sink/source @25°C \n• dV/dt transient immunity ±100 V/ns in full temperature range \n• Overall input-output propagation delay: 75 ns \n• Separate sink and source option for easy gate driving configuration \n• 4 A Miller CLAMP dedicated pin option \n• UVLO function• Gate driving voltage up to 26 V \n• 3.3 V, 5 V TTL/CMOS inputs with hysteresis \n• Temperature shut-down protection \n• Standby function \n• 6 kV galvanic isolation \n• Wide body SO-8W package;

The STGAP2SICS is a single gate driver which provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry.\n\n The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device is available in two different configurations. The configuration with separated output pins allows to independently optimize turn-on and turn-off by using dedicated gate resistors. The configuration featuring single output pin and Miller CLAMP function prevents gate spikes during fast commutations in half-bridge topologies. Both configurations provide high flexibility and bill of material reduction for external components.\n\n The device integrates protection functions: UVLO with optimized value for SiC MOSFETs and thermal shut down are included to facilitate the design of highly reliable systems. Dual input pins allow the selection of signal polarity control and implementation of HW interlocking protection to avoid cross-conduction in case of controller malfunction. The input to output propagation delay is less than 75 ns, which delivers high PWM control accuracy. A standby mode is available to reduce idle power consumption.\n\n

STGAP2SICSA

Galvanically isolated 4 A single gate driver for SiC MOSFETs; • AEC-Q100 qualified \n• High voltage rail up to 1200 V \n• Driver current capability: 4 A sink/source @25°C \n• 100 V/ns Common Mode Transient Immunity (CMTI) \n• Overall input-output propagation delay: 45 ns \n• Rail-to-rail outputs \n• 4 A Miller CLAMP dedicated pin \n• UVLO function• Gate driving voltage up to 26 V \n• 3.3 V, 5 V TTL/CMOS inputs with hysteresis \n• Temperature shut-down protection \n• Standby function \n• 6 kV galvanic isolation \n• Wide body SO-8W package \n• UL 1577 recognized;

The STGAP2SICSA is a single gate driver which provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry.\n\n The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device has a single output pin and Miller CLAMP function that prevents gate spikes during fast commutations in half-bridge topologies. This configuration provides high flexibility and bill of material reduction for external components. \n\n The device integrates protection functions: UVLO with optimized value for SiC MOSFETs and thermal shut down are included to facilitate the design of highly reliable systems. Dual input pins allow the selection of signal polarity control and implementation of HW interlocking protection to avoid cross-conduction in case of controller malfunction. The input to output propagation delay is less than 45 ns, which delivers high PWM control accuracy. A standby mode is available to reduce idle power consumption.\n\n

STGAP2SICSCTR

Galvanically isolated 4 A single gate driver for SiC MOSFETs

Features •Highvoltagerailupto1200V •Drivercurrentcapability:4Asink/source@25°C •dV/dttransientimmunity±100V/nsinfulltemperaturerange •Overallinput-outputpropagationdelay:75ns •Separatesinkandsourceoptionforeasygatedrivingconfiguration •4AMillerCLAMP

STGAP2SM

STGAP2S

Features •Highvoltagerailupto1700V •Drivercurrentcapability:4Asink/source@25°C •dV/dttransientimmunity±100V/nsinfulltemperaturerange •Overallinput-outputpropagationdelay:75ns •Separatesinkandsourceoptionforeasygatedrivingconfiguration •4AMillerCLAMP

STGAP2SMTR

STGAP2S

Features •Highvoltagerailupto1700V •Drivercurrentcapability:4Asink/source@25°C •dV/dttransientimmunity±100V/nsinfulltemperaturerange •Overallinput-outputpropagationdelay:75ns •Separatesinkandsourceoptionforeasygatedrivingconfiguration •4AMillerCLAMP