SN74SSTVF16859中文资料具有 SSTL_2 输入和输出的 500MHz、13 位至 26 位寄存缓冲器数据手册TI规格书

描述 Description

This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET)\\ input. All outputs are edge-controlled LVCMOS circuits optimized for unterminated DIMM loads.

The SN74SSTVF16859 operates from a differential clock (CLK and CLK\\). Data are registered at the crossing of CLK going high and CLK\\ going low.

The device supports low-power standby operation. When RESET\\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\\ input always must be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET\\ must be held in the low state during power up.

特性 Features

• Member of the Texas Instruments Widebus™ Family
• Operates at 2.5 V to 2.7 V for PC3200 (QFN Package)
• 600 ps Faster (Simultaneous Switching) Than the JEDEC Standard SSTV16859 in PC2700 DIMM Applications
• Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line
• Supports SSTL_2 Data Inputs
• Supports LVCMOS Switching Levels on the RESET\\ Input
• Pinout Optimizes DIMM PCB Layout
• ESD Protection Exceeds JESD22
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.