SN74SSTVF16857中文资料具有 SSTL_2 输入和输出的 14 位寄存缓冲器数据手册TI规格书

描述 Description

This 14-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.
All inputs are SSTL_2, except the LVCMOS reset (RESET)\\ input. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_2 Class I specifications.
The SN74SSTVF16857 operates from a differential clock (CLK and CLK\\). Data are registered at the crossing of CLK going high and CLK\\ going low.
The device supports low-power standby operation. When RESET\\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\\ is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET\\ input always must be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET\\ must be held in the low state during power up.

特性 Features

• Member of the Texas Instruments Widebus™ Family
• Pinout and Functionality Compatible With JEDEC Standard SSTV16857
• Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated DIMM Load
• Supports SSTL_2 Data Inputs
• Supports LVCMOS Switching Levels on the RESET\\ Input
• Flow-Through Architecture Optimizes PCB Layout
• ESD Protection Exceeds JESD 22
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)
Widebus is a trademark of Texas Instruments.