SN74SSTV32852-EP中文资料具有 Sstl_2 输入和输出的增强型产品 24 位至 48 位寄存缓冲器数据手册TI规格书

特性 Features

·Controlled Baseline·One Assembly/Test Site, One Fabrication Site

·Extended Temperature Performance of -40°C to 85°C
·Enhanced Diminishing Manufacturing Sources (DMS) Support
·Enhanced Product-Change Notification
·Qualification Pedigree

·Member of the Texas Instruments Widebus™ Family
·1-to-2 Outputs Support Stacked DDR DIMMs
·Supports SSTL_2 Data Inputs
·Outputs Meet SSTL_2 Class II Specifications
·Differential Clock (CLK and CLK) Inputs
·Supports LVCMOS Switching Levels on the RESET Input
·RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
·Pinout Optimizes DIMM PCB Layout
·One Device Per DIMM Required
·Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
·ESD Protection Exceeds JESD 22·2000-V Human-Body Model (A114-A)
·1000-V Charged-Device Model (C101)


Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.Widebus is a trademark of Texas Instruments.DESCRIPTION/ORDERING INFORMATIONThis 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible. The SN74SSTV32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.