SN74LVC2G125中文资料具有三态输出的 2 通道、1.65V 至 5.5V 缓冲器数据手册TI规格书

描述 Description

The SN74LVC2G125 device is a dual bus buffer gate, designed for 1.65-V to 5.5-V VCC operation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

特性 Features

• ESD Protection Exceeds JESD 22
• 1000-V Charged-Device Model
• Available in the Texas Instruments NanoFree™ Package
• Inputs Accept Voltages to 5.5 V
• Low Power Consumption, 10-µA Max ICC
• Typical VOLP (Output Ground Bounce) CC = 3.3 V, TA = 25°C
• Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II