SN74LV8154-EP中文资料具有三态输出寄存器的增强型产品双路 16 位二进制计数器数据手册TI规格书

描述 Description

The SN74LV8154 is a dual 16 bit binary counter with 3-state output registers, designed for 2-V to 5.5-V VCC operation.
This 16 bit counter (A or B) feeds a 16 bit storage register and each storage register is further divided into an upper byte and lower byte. The GAL, GAU, GBL, and GBU inputs are used to select the byte that needs to be output at Y0-Y7. CLKA is the clock for A counter and CLKB is the clock for B counter. RCLK is the clock for the A and B storage registers. All three clock signals are positive-edge triggered.
A 32 bit counter can be realized by connecting CLKA and CLKB together and by connecting RCOA to CLKBEN.
To ensure the high-impedance state during power up or power down, GAL, GAU, GBL, and GBU should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

特性 Features

• Controlled Baseline
• One Test Site
• Extended Temperature Performance of -55°C to 125°C
• Enhanced Product-Change Notification
• Can Be Used as Two 16 Bit Counters or a Single 32 Bit Counter
• Max tpd of 25 ns at 5 V (RCLK to Y)
• Typical VOHV (Output VOH Undershoot) >4.4 V at VCC = 5 V, TA = 25°C
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.