SN74LV595A-Q1中文资料具有三态输出寄存器的汽车类 8 位移位寄存器数据手册TI规格书

描述 Description

The SN74LV595A is an 8-bit shift register designed for 2-V to 5.5-V VCC operation. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable (OE) input is high, all outputs except QH' are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

特性 Features

• Qualified for Automotive Applications
• Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval
• 2-V to 5.5-V VCC Operation
• Typical VOLP (Output Ground Bounce) CC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) > 2.3 V at VCC = 3.3 V, TA = 25°C
• Supports Mixed-Mode Voltage Operation on All Ports
• 8-Bit Serial-In, Parallel-Out Shift
• Ioff Supports Partial-Power-Down Mode Operation
• Shift Register Has Direct Clear