SN74LV8154中文资料具有三态输出寄存器的双路 16 位二进制计数器数据手册TI规格书

描述 Description

The SN74LV8154 device is a dual 16-bit binary counter with 3-state output registers, designed for 2-V to 5.5-V VCC operation.
The counters have dedicated clock inputs. The counters share a clocked storage register to sample and save the counter contents. Both counters share an asynchronous clear input. The 32-bit storage register can be mapped on the output bus 8-bits at a time. Four bus reads are needed to access the contents of both stored counts. The two counters can be chained by connecting CLKBEN to RCOA. All clocks are positive edge triggered. All other inputs are active low.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
For all available packages, see the orderable addendum at the end of the data sheet.

特性 Features

• Can Be Used as Two 16-Bit Counters or a Single 32-Bit Counter
• 2-V to 5.5-V VCC Operation
• Typical VOLP (Output Ground Bounce) CC = 5 V, TA = 25°C
• Ioff Supports Partial-Power-Down Mode Operation
• ESD Protection Exceeds JESD 22
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)