SM320VC33-EP中文资料增强型产品 C33 浮点 DSP数据手册TI规格书

描述 Description

The SM320VC33-EP DSP is a 32-bit, floating-point processor manufactured in 0.18-µm four-level-metal CMOS (TImeline) technology. The SM320VC33-EP is part of the SM320C3x™ generation of DSPs from Texas Instruments.

The SM320C3x internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 150 million floating-point operations per second (MFLOPS). The SM320VC33-EP optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.

The SM320VC33-EP can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are the results of these features.

General-purpose applications are greatly enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, one external interface port, two timers, one serial port, and multiple-interrupt structure. The SM320C3x supports a wide variety of system applications from host processor to dedicated coprocessor. High-level-language support is easily implemented through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.

特性 Features

• Controlled Baseline
• Extended Temperature Performance of –40°C to 100°C (A Suffix), and –55°C to 125°C (M Suffix)
• Enhanced Product Change Notification
• High-Performance Floating-Point Digital Signal Processor (DSP):
• 17-ns Instruction Cycle Time
• 60 Million Instructions Per Second (MIPS)
• SM320VC33-150EP (GNM Suffix)
• 150 Million Floating-Point Operations Per Second (MFLOPS)
• 34K × 32-Bit (1.1M-bit) On-Chip Words of Dual-Access Static Random-Access Memory (SRAM) Configured in 2 × 16K plus 2 × 1K Blocks to improve Internal Performance
• Very Low Power: eff-Effective Gate Length) TImeline™ Technology by Texas Instruments (TI)
• One Serial Port
• Direct Memory Access (DMA)    Coprocessor for Concurrent I/O and CPU Operation
• 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix) and 144-Pin Non-hermetic Ceramic Ball Grid Array (CBGA) (GNM Suffix)
• Two Low-Power Modes
• Parallel Arithmetic/Logic Unit (ALU) and Multiplier Execution in a Single Cycle
• Zero-Overhead Loops With Single-Cycle Branches
• Interlocked Instructions for Multiprocessing Support
• 1.8-V (Core) and 3.3-V (I/O) Supply Voltages
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. TImeline and SM320C3x are trademarks of Texas Instruments. Other trademarks are the property of their respective owners.