SM320DM355-EP中文资料增强型产品数字媒体 DM355 处理器数据手册TI规格书

描述 Description

The DM355 is a highly integrated, programmable platform for digital still camera, digital photo frames, IP security cameras, 4-channel digital video recorders, video door bell application, and other low cost portable digital video applications. Designed to offer portable video designers and manufacturers the ability to produce affordable portable digital video solutions with high picture quality, the DM355 combines high performance MPEG4 HD (720p) codecs and JPEG codecs up to 50M pixels per second, high quality, and low power consumption at a very low price point. The DM355 also enables seamless interface to most additional external devices required for a complete digital camera implementation. The interface is flexible enough to support various types of CCD and CMOS sensors, signal conditioning circuits, power management, DDR/mDDR memory, SRAM, NAND, shutter, Iris and auto-focus motor controls, etc.

The DM355 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates:

A coprocessor 15 (CP15) and protection module Data and program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). DM355 performance is enhanced by its MPEG4/JPEG coprocessor. The MPEG4/JPEG coprocessor performs the computational operations required for image processing; JPEG compression and MPEG4 video and imaging standard. The MPEG4/JPEG coprocessor supports MPEG4 SP at HD (720p), D1, VGA, SIF encode/decode resolutions and JPEG encode/decode up to 50M pixels per second.

The DM355 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:

A Video Processing Front-End (VPFE) A Video Processing Back-End (VPBE) The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE provides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output.

The DM355 peripheral set includes:

An inter-integrated circuit (I2C) Bus interface Two audio serial ports (ASP) Three 64-bit general-purpose timers each configurable as two independent 32-bit timers A 64-bit watchdog timer Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals Three UARTs with hardware handshaking support on one UART Three serial port Interfaces (SPI) Four pulse width modulator (PWM) peripherals Four real time out (RTO) outputs Two Multi-Media Card / Secure Digital (MMC/SD/SDIO) interfaces Wireless interfaces (Bluetooth, WLAN, WUSB) through SDIO A USB 2.0 full and high-speed device and host interface Two external memory interfaces: An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as NAND and OneNAND, A high speed synchronous memory interface for DDR2/mDDR. For software development support the DM355 has a complete set of ARM development tools which ninclude: C compilers, assembly optimizers to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

特性 Features

• High-Performance Digital Media System-on-Chip
• Fully Software-Compatible With ARM9™
• ARM926EJ-S Core
• DSP Instruction Extensions and Single Cycle MAC
• EmbeddedICE-RT™ Logic for Real-Time Debug
• ARM9 Memory Architecture
• 8K-Byte Data Cache
• 8K-Byte ROM
• MPEG4/JPEG Coprocessor
• MPEG4 SP Codec at HD (720p), D1, VGA, SIF
• Video Processing Subsystem
• Hardware IPIPE for Real-Time Image Processing
• 16-/8-bit Generic YcBcR-4:2 Interface (BT.601)
• Up to 75-MHz Pixel Clock
• Resize Engine
• Separate Horizontal/Vertical Control
• Back End Provides:
• Composite NTSC/PAL video encoder output
• BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
• External Memory Interfaces (EMIFs)
• Asynchronous16-/8-bit Wide EMIF (AEMIF)
• NAND (8-/16-bit Wide Data)
• Flash Card Interfaces
• SmartMedia
• Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
• USB 2.0 Full and High-Speed Device
• Three 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
• Three UARTs (One fast UART with RTS and CTS Flow Control)
• One Master/Slave Inter-Integrated Circuit (I2C) Bus®
• I2S and TDM I2S
• S/PDIF via Software
• SPI Protocol (Master Mode Only)
• Four Pulse Width Modulator (PWM) Outputs
• Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
• Configurable Power-Saving Modes
• Flexible PLL Clock Generators
• IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
• Device Revision ID Readable by ARM
• 337-Pin Ball Grid Array (BGA) Package (GCE Suffix), 0.65-mm Ball Pitch
• 3.3-V and 1.8-V I/O, 1.3-V Internal
• Controlled Baseline
• One Fabrication Site
• Extended Product Life Cycle
• Product Traceability


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