SM320C6712D-EP数据手册TI中文资料规格书

描述 Description

The 320C67x™ DSPs (including the SM320C6712-EP, SM320C6712C-EP, SM320C6712D-EP devices) are members of the floating-point DSP family in the TMS320C6000™ DSP platform. The C6712, C6712C, and C6712D devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 1000 million floating-point operations per second (MFLOPS) at a clock rate of 167 MHz, the C6712C/C6712D device is the lowest-cost DSP in the C6000™ DSP platform. The C6712C/C6712D DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6712C/C6712D can produce two MACs per cycle for a total of 300 MMACS.

With performance of up to 600 million floating-point operations per second (MFLOPS) at a clock rate of 100 MHz, the C6712 device also offers cost-effective solutions to high-performance DSP programming challenges. The C6712 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6712 can produce two multiply-accumulates (MACs) per cycle for a total of 200 million MACs per second (MMACS).

The C6712/C6712C/C6712D uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, and a glueless 16-bit external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals. The C6712C device also includes a dedicated general-purpose input/output (GPIO) peripheral module.

The C6712/C6712C/C6712D DSPs also have application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6712/C6712C/C6712D has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

特性 Features

• Controlled Baseline
• One Assembly/Test Site, One Fabrication Site

• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree
• Low-Price/High-Performance Floating-Point Digital Signal Processors (DSPs): 320C67x™ (SM320C6712, C6712C, C6712D)
• Eight 32-Bit Instructions/Cycle
• 100-, 167-MHz Clock Rates
• 10-, 6-ns Instruction Cycle Times
• 600, 1000 MFLOPS

• Advanced Very Long Instruction Word (VLIW) C67x™ DSP Core
• Eight Highly Independent Functional Units:
• Four ALUs (Floating- and Fixed-Point)
• Two ALUs (Fixed-Point)
• Two Multipliers (Floating- and Fixed-Point)

• Load-Store Architecture With 32 32-Bit General-Purpose Registers
• Instruction Packing Reduces Code Size
• All Instructions Conditional

• Instruction Set Features
• Hardware Support for IEEE Single-Precision and Double-Precision Instructions
• Byte-Addressable (8-, 16-, 32-Bit Data)
• 8-Bit Overflow Protection
• Saturation
• Bit-Field Extract, Set, Clear
• Bit-Counting
• Normalization

• Device Configuration
• Boot Mode: 8- and 16-Bit ROM Boot
• Endianness: Little Endian (12/12C) Little Endian, Big Endian (12D)

• L1/L2 Memory Architecture
• 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
• 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
• 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)

• Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
• 16-Bit External Memory Interface (EMIF)
• Glueless Interface to Asynchronous Memories: SRAM and EPROM
• Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
• 256M-Byte Total Addressable External Memory Space

• Two Multichannel Buffered Serial Ports (McBSPs)
• Direct Interface to T1/E1, MVIP, SCSA Framers
• ST-Bus-Switching Compatible
• Up to 256 Channels Each
• AC97-Compatible
• Serial-Peripheral-Interface (SPI) Compatible (Motorola™)

• Two 32-Bit General-Purpose Timers
• Flexible Phase-Locked-Loop (PLL) Clock Generator [C6712]
• Flexible Software Configurable PLL-Based Clock Generator Module [C6712C/C6712D]
• A Dedicated General-Purpose Input/Output (GPIO) Module With 5 Pins [12C/12D]
• IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
• CMOS Technology
• 0.13-µm/6-Level Copper Metal Process (C6712C/C6712D)
• 0.18-µm/5-Level Metal Process (C6712)

320C67x and C67x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc.