SM320F2812-EP中文资料具有 150MHz 频率、256KB 闪存、EMIF 的 C2000™ 增强型产品 32 位 MCU数据手册TI规格书

描述 Description

The SM320F2810-EP, SM320F2811-EP, SM320F2812-EP, SM320C2810-EP, SM320C2811-EP, and SM320C2812-EP devices, members of the TMS320C28x™ DSP generation, are highly integrated, high-performance solutions for demanding control applications. The functional blocks and the memory maps are described in Section 3, Functional Overview.

Throughout this document, SM320F2810-EP, SM320F2811-EP, and SM320F2812-EP are abbreviated as F2810, F2811, and F2812, respectively. F281x denotes all three Flash devices. SM320C2810-EP, SM320C2811-EP, and SM320C2812-EP are abbreviated as C2810, C2811, and C2812, respectively. C281x denotes all three ROM devices. 2810 denotes both F2810 and C2810 devices; 2811 denotes both F2811 and C2811 devices; and 2812 denotes both F2812 and C2812 devices.

特性 Features

• Controlled Baseline
• Extended Temperature Performance of –55°C to 125°C
• Enhanced Product-Change Notification
• High-Performance Static CMOS Technology
• Low-Power (1.8-V Core @135 MHz, 1.9-V Core @150 MHz, 3.3-V I/O) Design
• JTAG Boundary Scan Support
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• 16 × 16 and 32 × 32 MAC Operations
• Harvard Bus Architecture
• Fast Interrupt Response and Processing
• 4M Linear Program/Data Address Reach
• 320F24x/LF240x Processor Source Code Compatible
• On-Chip Memory
• ROM Devices: Up to 128K × 16 ROM
• L0 and L1: 2 Blocks of 4K × 16 Each Single-Access RAM (SARAM)
• M0 and M1: 2 Blocks of 1K × 16 Each SARAM
• Boot ROM (4K × 16)
• Standard Math Tables
• External Interface (2812)
• Programmable Wait States
• Three Individual Chip Selects
• Clock and System Control
• On-Chip Oscillator
• Three External Interrupts
• Three 32-Bit CPU-Timers
• Protects Flash/ROM/OTP and L0/L1 SARAM
• Motor Control Peripherals
• Compatible to 240xA Devices
• Serial Port Peripherals
• Two Serial Communications Interfaces (SCIs), Standard UART
• Multichannel Buffered Serial Port (McBSP)
• 12-Bit ADC, 16 Channels
• Two Sample-and-Hold
• Fast Conversion Rate: 80 ns/12.5 MSPS
• Up to 56 General Purpose I/O (GPIO) Pins
• Analysis and Breakpoint Functions
• Development Tools Include
• Code Composer Studio™ IDE
• Low-Power Modes and Power Savings
• Disable Individual Peripheral Clocks
• Package Options
• 176-Pin Low-Profile Quad Flatpack (LQFP) (PGF) (2812)
• IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port