SM320F2812数据手册TI中文资料规格书

描述 Description

The SM320F2812 device, member of the C28x™ DSP generation, is a highly integrated, high-performance solution for demanding control applications. The functional blocks and the memory maps are described in Section 3, Functional Overview.

Throughout this document, SM320F2812 is abbreviated as F2812.

The SM320F2812 device, member of the C28x™ DSP generation, is a highly integrated, high-performance solution for demanding control applications. The functional blocks and the memory maps are described in Section 3, Functional Overview.

Throughout this document, SM320F2812 is abbreviated as F2812.

特性 Features

• High-Performance Static CMOS Technology
• 150 MHz (6.67-ns Cycle Time)
• Low-Power (1.8-V Core at 135 MHz, 1.9-V Core at 150 MHz, 3.3-V I/O) Design
• 3.3-V Flash Voltage

• JTAG Boundary Scan Support
• High-Performance 32-Bit CPU (TMS320C28x)
• 16 x 16 and 32 x 32 MAC Operations
• 16 x 16 Dual MAC
• Harvard Bus Architecture
• Atomic Operations
• Fast Interrupt Response and Processing
• Unified Memory Programming Model
• 4M Linear Program Address Reach
• 4M Linear Data Address Reach
• Code-Efficient (in C/C++ and Assembly)
• TMS320F24x/LF240x Processor Source Code Compatible

• On-Chip Memory
• Flash Devices: Up to 128K x 16 Flash (Four 8K x 16 and Six 16K x 16 Sectors)
• ROM Devices: Up to 128K x 16 ROM
• 1K x 16 OTP ROM
• L0 and L1: 2 Blocks of 4K x 16 Each Single-Access RAM (SARAM)
• H0: 1 Block of 8K x 16 SARAM
• M0 and M1: 2 Blocks of 1K x 16 Each SARAM

• Boot ROM (4K x 16)
• With Software Boot Modes
• Standard Math Tables

• External Interface
• Up to 1M Total Memory
• Programmable Wait States
• Programmable Read/Write Strobe Timing
• Three Individual Chip Selects

• Clock and System Control
• Dynamic PLL Ratio Changes Supported
• On-Chip Oscillator
• Watchdog Timer Module

• Three External Interrupts
• Peripheral Interrupt Expansion (PIE) Block That Supports 45 Peripheral Interrupts
• 128-Bit Security Key/Lock
• Protects Flash/ROM/OTP and L0/L1 SARAM
• Prevents Firmware Reverse Engineering

• Three 32-Bit CPU-Timers
• Motor Control Peripherals
• Two Event Managers (EVA, EVB)
• Compatible to 240xA Devices

• Serial Port Peripherals
• Serial Peripheral Interface (SPI)
• Two Serial Communications Interfaces (SCIs), Standard UART
• Enhanced Controller Area Network (eCAN)
• Multichannel Buffered Serial Port (McBSP) With SPI Mode

• 12-Bit ADC, 16 Channels
• 2 x 8 Channel Input Multiplexer
• Two Sample-and-Hold
• Single/Simultaneous Conversions
• Fast Conversion Rate: 80 ns/12.5 MSPS

• Up to 56 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins
• Advanced Emulation Features
• Analysis and Breakpoint Functions
• Real-Time Debug via Hardware

• Development Tools Include
• ANSI C/C++ Compiler/Assembler/Linker
• Supports TMS320C24x™/240x Instructions
• Code Composer Studio™ IDE
• DSP/BIOS™
• JTAG Scan Controllers [Texas Instruments (TI) or Third-Party]
• Evaluation Modules
• Broad Third-Party Digital Motor Control Support

• Low-Power Modes and Power Savings
• IDLE, STANDBY, HALT Modes Supported
• Disable Individual Peripheral Clocks

• Package Options
• 172-Pin Ceramic Quad Flatpack (HFG)

• Temperature Options:
• M: –55°C to 125°C (HFG)

TMS320C24x, Code Composer Studio, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments. IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port TMS320C28x is a trademark of Texas Instruments.