SLG47105开发板套件编程器的评估板-嵌入式-复杂逻辑器件（FPGA,CPLD）规格书PDF中文资料

Key Features

 Two Power Supply Inputs:

 2.5 V (±8 ) to 5.0 V (±10 ) VDD

 3.3 V (±9 ) to 12.0 V (±10 ) VDD2

 Four High Voltage High Current Drive GPOs

 Dual/Single Full Bridge Driver Option

 Quad/Dual/Single Half Bridge Driver Option

 Slew Rate Modes:

 Motor Driver Mode

 Pre-Driver (MOSFET Driver) Mode

 SLEEP Function

 Low RDS ON High Side + Low Side resistance = 0.4 W

 2 A Peak, 1.5 A RMS per Full Bridge (at VDD2 = 5 V,

T = 25 °C) (Note 1)

 4 A Peak, 3 A RMS per two Full Bridge connected in

parallel (at VDD2 = 5 V, T = 25 °C) (Note 1)

 2 A Peak, 1.5 A RMS per Half Bridge GPO

(at VDD2 = 5 V, T = 25 °C) (Note 1)

 Integrated Protections:

Over Current Protection (OCP)

Short Circuit Protection

Under-Voltage Lockout (UVLO)

Thermal Shutdown (TSD)

 SENSE_A, SENSE_B Inputs that are connected to the

Current Comparators for Current Control

 Fault Signal Indicator individual per Full Bridge:

OCP

UVLO

TSD

 Differential Amplifier with Integrator and Comparator for Motor Speed Control Function

 Two Current Sense Comparators with Dynamical Vref Mode

 Two High-Speed General Purpose ACMPs

 Modes: UVLO, OCP, TSD, Voltage Monitor, Current Monitor