SLG47004开发板套件编程器的评估板-嵌入式-复杂逻辑器件（FPGA,CPLD）规格书PDF中文资料

 Two Programmable Bandwidth Op Amps

 3-Op Amp Instrumentation Amplifier Function

(including Additional Internal Op Amp)

 Rail to Rail Input

 Low Quiescent Current

 Low Offset Voltage

 Analog Comparator Mode

 Optional Vref Voltage Connection for Input Pins

 Two 1024 Position Digital Rheostats

 User Defined Auto-Trim Option

 Manual Control Option

 I2C Control Option

 Potentiometer Mode

 Two Single-Pole/Single-Throw Analog Switches

 Voltage or Current Source/Sink Mode

 One Low Offset Chopper Comparator

 Two Low Power General Purpose ACMPs

 ACMP Sampling Mode

 Hysteresis with Independently-Selectable Thresholds

 Three Voltage References

 Two ACMP Vref Output Buffers

 One High Drive Buffer

 Thirteen Combination Function Macrocells

 Three Selectable DFF/LATCH or 2-bit LUTs

 One Selectable Programmable Pattern Generator or

2-bit LUT

 Seven Selectable DFF/LATCH or 3-bit LUTs

 One Selectable Pipe Delay or Ripple Counter or