36-Mbit QDR™ II SRAM 4-word Burst Architecture (2.5 Cycle Read latency) with ODT

Description The RMQSDA3636DGBA is a 1,048,576-word by 36-bit and the RMQSDA3618DGBA is a 2,097,152-word by 18-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and

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36-Mbit QDR??II SRAM 4-word Burst Architecture (2.5 Cycle Read latency) with ODT

文件：898.75 Kbytes 页数：31 Pages

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36-Mbit QDR??II SRAM 4-word Burst Architecture (2.5 Cycle Read latency) with ODT

文件：898.75 Kbytes 页数：31 Pages

RENESAS

瑞萨

36-Mbit QDR??II SRAM 4-word Burst Architecture (2.5 Cycle Read latency) with ODT

文件：898.75 Kbytes 页数：31 Pages

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36-Mbit QDR™ II SRAM 4-word Burst Architecture (2.5 Cycle Read latency) with ODT

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36-Mbit QDR™ II+ SRAM 4-word Burst Architecture (2.5 Cycle Read latency) with ODT

The RMQSDA3636DGBA is a 1, 048, 576-word by 36-bit and the RMQSDA3618DGBA is a 2, 097, 152-word by 18-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst count • Power Supply 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)\n• Clock Fast clock cycle time for high bandwidth Two input clocks (K and /K) for precise DDR timing at clock rising edges only Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems Clock-stop capability with ;

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