36-Mbit QDR??II SRAM 4-word Burst Architecture (2.0 Cycle Read latency) with ODT

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18-Mbit DDR™ II SRAM 2-word Burst

The RMQC4A1836DGBA is a 524, 288-word by 36-bit and the RMQC4A1818DGBA is a 1, 048, 576-word by 18-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. • Power Supply 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)\n• I/O Common data input/output bus Pipelined double data rate operation HSTL I/O User programmable output impedance PLL circuitry for wide output data valid window and future frequency scaling\n• Package 165 FBGA package (13 x 15 x 1.;

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18-Mbit DDR™ II SRAM 2-word Burst

The RMQC4A1836DGBA is a 524, 288-word by 36-bit and the RMQC4A1818DGBA is a 1, 048, 576-word by 18-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. • Power Supply 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)\n• Clock Fast clock cycle time for high bandwidth Two input clocks (K and /K) for precise DDR timing at clock rising edges only Two input clocks for output data (C and /C) to minimize clock skew and flight time mismatches Two output ec;

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18-Mbit DDR™ II SRAM 2-word Burst

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