LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

FEATURES: • 5V operation • 2xQ output, Q/2 output, Q output • Outputs tri-state while RST low • Internal loop filter RC network • Low noise TTL level outputs •

文件：241.66 Kbytes 页数：8 Pages

RENESAS

瑞萨

LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

FEATURES: • 5V operation • 2xQ output, Q/2 output, Q output • Outputs tri-state while RST low • Internal loop filter RC network • Low noise TTL level outputs •

文件：241.66 Kbytes 页数：8 Pages

RENESAS

瑞萨

LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

FEATURES: • 5V operation • 2xQ output, Q/2 output, Q output • Outputs tri-state while RST low • Internal loop filter RC network • Low noise TTL level outputs •

文件：241.66 Kbytes 页数：8 Pages

RENESAS

瑞萨

丝印：K02；Package：SOT-25；2.5V Drive NchNch MOS FET

■ MOSFETs ● Small Signal MOSFET Series ● Middle Power MOSFET Series ● Power MOSFET Series ■ Selector Guide for Automotive MOSFETs (AEC-Q101) ■ Bipolar Transistors (Surface mount type) ■ Transistor Array ■ Complex Bipolar Transistors ■ Digital Transistors ■ Complex Digital Transis

文件：67.16 Kbytes 页数：3 Pages

ROHM

罗姆

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件：98.35 Kbytes 页数：12 Pages

IDT

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件：98.35 Kbytes 页数：12 Pages

IDT

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件：98.35 Kbytes 页数：12 Pages

IDT

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件：98.35 Kbytes 页数：12 Pages

IDT

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件：98.35 Kbytes 页数：12 Pages

IDT

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件：98.35 Kbytes 页数：12 Pages

IDT