首页 >QS5LV919>规格书列表

型号下载 订购功能描述制造商 上传企业LOGO

QS5LV919

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件:98.35 Kbytes 页数:12 Pages

IDT

QS5LV919

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION:\nThe QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure < 300 ps skew between the Q0-Q4, and Q/2 outputs. The QS5LV919 includes a

Renesas

瑞萨

QS5LV919100J

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件:98.35 Kbytes 页数:12 Pages

IDT

QS5LV919100Q

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件:98.35 Kbytes 页数:12 Pages

IDT

QS5LV919133J

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件:98.35 Kbytes 页数:12 Pages

IDT

QS5LV919133Q

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件:98.35 Kbytes 页数:12 Pages

IDT

QS5LV919160J

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件:98.35 Kbytes 页数:12 Pages

IDT

QS5LV919160Q

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件:98.35 Kbytes 页数:12 Pages

IDT

QS5LV91955J

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件:98.35 Kbytes 页数:12 Pages

IDT

QS5LV91955Q

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件:98.35 Kbytes 页数:12 Pages

IDT

详细参数

  • 型号:

    QS5LV919

  • 制造商:

    IDT

  • 制造商全称:

    Integrated Device Technology

  • 功能描述:

    3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

供应商型号品牌批号封装库存备注价格
IDT
24+
SSOP28
35
询价
IDT
25+
SSOP28
2568
原装优势!绝对公司现货
询价
IDT
23+
2800
正品原装货价格低
询价
IDT
2025+
SSOP28
3827
全新原厂原装产品、公司现货销售
询价
QS
2023+
PLCC28
50000
原装现货
询价
QS
24+
PLCC28
3000
只做原装正品现货 欢迎来电查询15919825718
询价
QUCKLOGIC
23+
PLCC28
7100
绝对全新原装!现货!特价!请放心订购!
询价
QS
25+
PLCC28
438
⊙⊙新加坡大量现货库存,深圳常备现货!欢迎查询!⊙
询价
QUALITYSEMI
24+
原封装
1580
原装现货假一罚十
询价
QS
00+
PLCC28
40
全新原装100真实现货供应
询价
更多QS5LV919供应商 更新时间2025-10-13 10:02:00