3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件：98.35 Kbytes 页数：12 Pages

IDT

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件：98.35 Kbytes 页数：12 Pages

IDT

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件：98.35 Kbytes 页数：12 Pages

IDT

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件：98.35 Kbytes 页数：12 Pages

IDT

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件：98.35 Kbytes 页数：12 Pages

IDT

24V, 5A, SINGLE PHASE INPUT

文件：838.88 Kbytes 页数：26 Pages

PULS

普尔世

24V, 100W, DC/DC CONVERTER

文件：798.87 Kbytes 页数：27 Pages

PULS

普尔世

24V, 3.8A, NEC CLASS 2, DEVICENET POWER SUPPLY

文件：686.34 Kbytes 页数：21 Pages

PULS

普尔世

AC-DC Power Supplies

文件：218.93 Kbytes 页数：2 Pages

TDK

东电化

AC-DC Power Supplies

文件：218.92 Kbytes 页数：2 Pages

TDK

东电化