PM8353中文资料4-Channel 1.0-1.25 Gbps Transceiver数据手册PMC-Sierra规格书

描述 Description

GENERAL DESCRIPTION
The QuadPHYTM is a Quad PHYsical layer transceiver ideal for systems requiring large numbers of point-to-point gigabit links. It provides four individual serial channels capable of operation at up to 1.25 Gbps each, which may be grouped together to form a single 5.0 Gbps bidirectional link. Each of the four primary channels has a corresponding secondary channel that can be enabled via the MDC/MDIO serial interface.FEATURES
• Four independent 1.0-1.25 Gbit/s transceivers
• Four secondary channels to support channel redundancy
• Ultra low power operation: 1.25 Watt typical
• Integrated serializer/deserializer, clock synthesis, clock recovery, and 8B/10B encode/decode logic
• Physical Coding Sublayer (PCS) logic for Gigabit Ethernet
• Selectable 8-bit, 10-bit, or IEEE 802.3z GMII parallel interface
• Optional Receive FIFOs which synchronize incoming data to local clock domain
• “Trunking” feature to de-skew and align received parallel data across four channels
• 100-156 MHz Single Data Rate (SDR) parallel transmit interface with clock forwarding
• 100-125 MHz SDR parallel receive interface
• Extensive control of loopback, BIST, and operating modes via 802.3 compliant MDC/MDIO serial interface
• Built-in packet generator/checker
• IEEE 1149.1 JTAG testing support
• IEEE 802.3z Gigabit Ethernet and ANSI X3T11 Fibre Channel support
• High speed outputs which feature programmable output current to directly drive dual-terminated line
• 2.5V, 0.25 micron CMOS technology with 3.3V tolerant I/O
• Direct interface to optical modules, coax, or serial backplanes
• Small footprint 19x19 mm, 289-pin PBGAAPPLICATIONS
• High speed serial backplanes
• Gigabit Ethernet links
• Fibre Channel links
• Intra-system interconnect
• ASIC to PMD link

特性 Features

• Four independent 1.0-1.25 Gbit/s transceivers
• Four secondary channels to support channel redundancy
• Ultra low power operation: 1.25 Watt typical
• Integrated serializer/deserializer, clock synthesis, clock recovery, and 8B/10B encode/decode logic
• Physical Coding Sublayer (PCS) logic for Gigabit Ethernet
• Selectable 8-bit, 10-bit, or IEEE 802.3z GMII parallel interface
• Optional Receive FIFOs which synchronize incoming data to local clock domain
• “Trunking” feature to de-skew and align received parallel data across four channels
• 100-156 MHz Single Data Rate (SDR) parallel transmit interface with clock forwarding
• 100-125 MHz SDR parallel receive interface
• Extensive control of loopback, BIST, and operating modes via 802.3 compliant MDC/MDIO serial interface
• Built-in packet generator/checker
• IEEE 1149.1 JTAG testing support
• IEEE 802.3z Gigabit Ethernet and ANSI X3T11 Fibre Channel support
• High speed outputs which feature programmable output current to directly drive dual-terminated line
• 2.5V, 0.25 micron CMOS technology with 3.3V tolerant I/O
• Direct interface to optical modules, coax, or serial backplanes
• Small footprint 19x19 mm, 289-pin PBGA