PM8351中文资料8-Channel 1.0-1.25 Gbps Transceiver数据手册Sierra规格书

描述 Description

GENERAL DESCRIPTION
The OctalPHYTM is an octal PHYsical layer transceiver ideal for systems requiring large numbers of point-to-point gigabit links. It provides eight individual serial channels capable of operation at up to 1.25 Gbps, which may be grouped together to form a single 12.5 Gbps bidirectional link.
The OctalPHY includes 8B/10B block coding logic (compliant with 802.3z Gigabit Ethernet and FibreChannel requirements) which produces run length limited data streams for serial transmission.FEATURES
• Eight independent 1.0-1.25 Gbit/s transceivers
• Ultra low power operation: 1.25 Watts typical
• Integrated serializer/deserializer, clock synthesis, clock recovery, and 8B/10B encode/decode logic
• Physical Coding Sublayer (PCS) logic for Gigabit Ethernet
• Optional receive FIFO which synchronizes incoming data to local clock domain
• Dual Data Rate (DDR) parallel interface with clock forwarding to halve ASIC terminal count and simplify timing
• Extensive control of loopback, BIST, and operating modes via 802.3 compliant MDC/MDIO serial interface
• Built-in packet generator/checker
• “Trunking” feature to de-skew and align received parallel data across eight channels
• IEEE 1149.1 JTAG testing support
• IEEE 802.3z Gigabit Ethernet and ANSI X3T11 FibreChannel support
• High speed outputs which feature programmable output current to directly drive dual-terminated line
• 2.5 V, 0.25 µ CMOS technology with 3.3V tolerant I/O
• Direct interface to optical modules, coax, or serial backplanes
• Small footprint 19x19 mm, 289-pin PBGAAPPLICATIONS
• High speed serial backplanes
• Gigabit Ethernet links
• FibreChannel links
• Intra-system interconnect
• ASIC to PMD link

特性 Features

• Eight independent 1.0-1.25 Gbit/s transceivers
• Ultra low power operation: 1.25 Watts typical
• Integrated serializer/deserializer, clock synthesis, clock recovery, and 8B/10B encode/decode logic
• Physical Coding Sublayer (PCS) logic for Gigabit Ethernet
• Optional receive FIFO which synchronizes incoming data to local clock domain
• Dual Data Rate (DDR) parallel interface with clock forwarding to halve ASIC terminal count and simplify timing
• Extensive control of loopback, BIST, and operating modes via 802.3 compliant MDC/MDIO serial interface
• Built-in packet generator/checker
• “Trunking” feature to de-skew and align received parallel data across eight channels
• IEEE 1149.1 JTAG testing support
• IEEE 802.3z Gigabit Ethernet and ANSI X3T11 FibreChannel support
• High speed outputs which feature programmable output current to directly drive dual-terminated line
• 2.5 V, 0.25 µ CMOS technology with 3.3V tolerant I/O
• Direct interface to optical modules, coax, or serial backplanes
• Small footprint 19x19 mm, 289-pin PBGA