PM8313-RI数据手册Sierra中文资料规格书

描述 Description

FEATURES
• Integrates a full featured M13 multiplexer and DS-3 framer in a single monolithic device.
• Supports the M23 or C-bit parity DS3 formats.
• Supports the M12 or G.747 formats allowing DS1 or E1 signals to be multiplexed into a DS3 signal.
•
• Allows the M12 stages to be bypassed allowing direct input of DS2 signals into the M23 multiplexer stage.
• Provides a generic microprocessor interface for configuration, control, and status monitoring.
• Low power CMOS technology.
• Packaged in a 208 pin Plastic Quad Flat Pack (PQFP) package.Each DS3 framer/performance monitor section:
• Frames to a DS3 signal with a maximum average reframe time of less than 1.5 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191 Section 5.2).
• Decodes a B3ZS-encoded signal and indicates line code violations. The definition of line code violation is software selectable.
• Detects and accumulates occurrences of excessive zeros and loss of signal.
• Provides indication of M-frame and M-subframe boundaries, and overhead bit positions in the DS3 stream.
• Detects the DS3 alarm indication signal (AIS) and idle signal. Detection algorithms operate correctly in the presence of a 10-3 bit error rate.
• Extracts valid X-bits and indicates far end receive failure. Accumulates up to 65,535 line code violation (LCV) events per second, 16,383 P-bit parity error events per second, 1023 F-bit or M-bit (framing bit) events per second, 65,535 excessive zero (EXZ) events per second, and when enabled for C-bit parity mode operation, up to 16,383 C-bit parity error events per second, and 16,383 far end block error (FEBE) events per second.
• Detects and validates bit-oriented codes in the C-bit parity far end alarm and control channel.
• Terminates the C-bit parity path maintenance data link with an integral HDLC receiver having a 4-byte deep FIFO buffer. Supports polled, interrupt-driven or DMA access.
• Optionally extracts the C-bit parity mode path maintenance data link signal and serializes it at 28.2 kbit/s.
• Extracts the X, P, M, F, C and stuff opportunity bits and serializes them at 526 kbit/s on a time division multiplex signal.Each DS3 transmit framer section:
• Provides the overhead bit insertion for a DS3 stream.
• Provides a bit serial clock and data interface, and allows the M-frame boundary and/or the overhead bit positions to be located via an external interface
• Provides optional insertion of the X, P, M, F, C, and stuff opportunity bits via a 526 kbit/s serial interface.
• Provides B3ZS encoding.
• Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS) and the idle signal when enabled by external inputs, or internal register bits.
• Provides diagnostic features to allow the generation of line code violation error events, parity error events, framing bit error events, and when enabled for the C-bit parity application, C-bit parity error events, and far end block error events.
• Inserts bit-oriented codes in the C-bit parity far end alarm and control channel.
• Optionally inserts the C-bit parity path maintenance data link with an integral HDLC transmitter. Supports polled, interrupt-driven, or DMA access.
• Optionally inserts the C-bit parity mode path maintenance data link signal from a 28.2 kbit/s serial input.APPLICATIONS
• M23 Based M13 Multiplexer
• C-Bit Parity Based M13 Multiplexer
• M23 Multiplexer
• M13 Multiplexer Supporting G.747 Tributary Format

特性 Features

• Integrates a full featured M13 multiplexer and DS-3 framer in a single monolithic device.
• Supports the M23 or C-bit parity DS3 formats.
• Supports the M12 or G.747 formats allowing DS1 or E1 signals to be multiplexed into a DS3 signal.
•
• Allows the M12 stages to be bypassed allowing direct input of DS2 signals into the M23 multiplexer stage.
• Provides a generic microprocessor interface for configuration, control, and status monitoring.
• Low power CMOS technology.
• Packaged in a 208 pin Plastic Quad Flat Pack (PQFP) package.Each DS3 framer/performance monitor section:
• Frames to a DS3 signal with a maximum average reframe time of less than 1.5 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191 Section 5.2).
• Decodes a B3ZS-encoded signal and indicates line code violations. The definition of line code violation is software selectable.
• Detects and accumulates occurrences of excessive zeros and loss of signal.
• Provides indication of M-frame and M-subframe boundaries, and overhead bit positions in the DS3 stream.
• Detects the DS3 alarm indication signal (AIS) and idle signal. Detection algorithms operate correctly in the presence of a 10-3 bit error rate.
• Extracts valid X-bits and indicates far end receive failure. Accumulates up to 65,535 line code violation (LCV) events per second, 16,383 P-bit parity error events per second, 1023 F-bit or M-bit (framing bit) events per second, 65,535 excessive zero (EXZ) events per second, and when enabled for C-bit parity mode operation, up to 16,383 C-bit parity error events per second, and 16,383 far end block error (FEBE) events per second.
• Detects and validates bit-oriented codes in the C-bit parity far end alarm and control channel.
• Terminates the C-bit parity path maintenance data link with an integral HDLC receiver having a 4-byte deep FIFO buffer. Supports polled, interrupt-driven or DMA access.
• Optionally extracts the C-bit parity mode path maintenance data link signal and serializes it at 28.2 kbit/s.
• Extracts the X, P, M, F, C and stuff opportunity bits and serializes them at 526 kbit/s on a time division multiplex signal.Each DS3 transmit framer section:
• Provides the overhead bit insertion for a DS3 stream.
• Provides a bit serial clock and data interface, and allows the M-frame boundary and/or the overhead bit positions to be located via an external interface
• Provides optional insertion of the X, P, M, F, C, and stuff opportunity bits via a 526 kbit/s serial interface.
• Provides B3ZS encoding.
• Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS) and the idle signal when enabled by external inputs, or internal register bits.
• Provides diagnostic features to allow the generation of line code violation error events, parity error events, framing bit error events, and when enabled for the C-bit parity application, C-bit parity error events, and far end block error events.
• Inserts bit-oriented codes in the C-bit parity far end alarm and control channel.
• Optionally inserts the C-bit parity path maintenance data link with an integral HDLC transmitter. Supports polled, interrupt-driven, or DMA access.
• Optionally inserts the C-bit parity mode path maintenance data link signal from a 28.2 kbit/s serial input.