Phase-Locked Loop Clock Driver

Product Description The PI6C2502 features a low-skew, low-jitter, phase-locked loop (PLL) clock driver. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. Product Features • High-Per

文件：371.09 Kbytes 页数：6 Pages

PERICOMPericom Semiconductor Corporation

百利通百利通半导体

Phase-Locked Loop Clock Driver

Product Description\nThe PI6C2502 features a low-skew, low-jitter, phase-locked loop (PLL) clock driver.  By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero.Product • High-Performance Phase-Locked-Loop Clock Distribution for Networking,\n• Synchronous DRAM modules for server/workstation/PC applications\n• Allows Clock Input to have Spread Spectrum modulation for EMI reduction\n• Zero Input-to-Output delay\n• Low jitter: Cycle-to-Cycle jitter ±100ps max.\n• On-c;

Diodes

美台半导体

Phase-Locked Loop Clock Driver

Product Description The PI6C2502A features a low-skew, low-jitter, phase-locked loop (PLL) clock driver. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. Product Features • High-Pe

文件：276.03 Kbytes 页数：4 Pages

PERICOMPericom Semiconductor Corporation

百利通百利通半导体

Phase-Locked Loop Clock Driver

Product Description The PI6C2502A features a low-skew, low-jitter, phase-locked loop (PLL) clock driver. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. Product Features • High-Pe

文件：276.03 Kbytes 页数：4 Pages

PERICOMPericom Semiconductor Corporation

百利通百利通半导体

Phase-Locked Loop Clock Driver

Product Description\nThe PI6C2502A features a low-skew, low-jitter, phase-locked loop (PLL) clock driver.  By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero.Product • High-Performance Phase-Locked-Loop Clock Distributionfor Networking,\n• Synchronous DRAM modules for server/workstation/PC applications\n• Allows Clock Input to have Spread Spectrum modulation for EMI reduction\n• Zero Input-to-Output delay\n• Low jitter: Cycle-to-Cycle jitter ±75ps max.\n• On-chi;

Diodes

美台半导体

Package：8-SOIC（0.154"，3.90mm 宽）；包装：管件 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC PLL CLOCK DRIVER 8-SOIC

PAM

龙鼎微

Package：8-SOIC（0.154"，3.90mm 宽）；包装：管件 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC PLL CLOCK DRIVER 8-SOIC

PAM

龙鼎微

Package：8-SOIC（0.154"，3.90mm 宽）；包装：管件 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC PLL CLOCK DRIVER 8-SOIC

PAM

龙鼎微