PI6C2502AW集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

Product Description

The PI6C2502A features a low-skew, low-jitter, phase-locked loop (PLL) clock driver. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero.

Product Features

• High-Performance Phase-Locked-Loop Clock Distributionfor Networking,

• Synchronous DRAM modules for server/workstation/PC applications

• Allows Clock Input to have Spread Spectrum modulation for EMI reduction

• Zero Input-to-Output delay

• Low jitter: Cycle-to-Cycle jitter ±75ps max.

• On-chip series damping resistor at clock output drivers for low noise and EMI reduction

• Operates at 3.3V VCC

• Wide range of Clock Frequencies 80 to 134 MHz

• Package: Plastic 8-pin SOIC Package (W)