PI6C2502A中文资料Phase-Locked Loop Clock Driver数据手册Diodes规格书

描述 Description

Product Description
The PI6C2502A features a low-skew, low-jitter, phase-locked loop (PLL) clock driver.  By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero.Product

特性 Features

• High-Performance Phase-Locked-Loop Clock Distributionfor Networking,
• Synchronous DRAM modules for server/workstation/PC applications
• Allows Clock Input to have Spread Spectrum modulation for EMI reduction
• Zero Input-to-Output delay
• Low jitter: Cycle-to-Cycle jitter ±75ps max.
• On-chip series damping resistor at clock output drivers for low noise and EMI reduction
• Operates at 3.3V VCC
• Wide range of Clock Frequencies 80 to 134 MHz
• Package: Plastic 8-pin SOIC Package (W)

简介

PI6C2502A属于集成电路（IC）的时钟发生器PLL频率合成器。由制造生产的PI6C2502A时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。