50-150 MHz 1:10 SDRAM clock driver

DESCRIPTION The PCK2510S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The P

文件：81.51 Kbytes 页数：10 Pages

PHI

飞利浦

66-150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver

DESCRIPTION Zero delay buffer to distribute an SSTL differential clock input pair to 10 SSTL_2 differential output pairs. Outputs are slope controlled. External feedback pin for synchronization of the outputs to the input. A CMOS style Enable/Disable pin is provided for low power disable. FEAT

文件：62.58 Kbytes 页数：8 Pages

PHI

飞利浦

66-150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver

DESCRIPTION Zero delay buffer to distribute an SSTL differential clock input pair to 10 SSTL_2 differential output pairs. Outputs are slope controlled. External feedback pin for synchronization of the outputs to the input. A CMOS style Enable/Disable pin is provided for low power disable. FEAT

文件：62.58 Kbytes 页数：8 Pages

PHI

飞利浦

Low voltage 1 : 18 clock distribution chip

General description The PCK942C is a 1 : 18 low voltage clock distribution chip with 2.5 V or 3.3 V LVCMOS output capabilities. The device is offered in two versions: the PCK942C has an LVCMOS input clock, while the PCK942P has an LVPECL input clock. The 18 outputs are 2.5 V or 3.3 V LVCMOS compa

文件：69.12 Kbytes 页数：11 Pages

恩XP

Low voltage 1 : 18 clock distribution chip

General description The PCK942C is a 1 : 18 low voltage clock distribution chip with 2.5 V or 3.3 V LVCMOS output capabilities. The device is offered in two versions: the PCK942C has an LVCMOS input clock, while the PCK942P has an LVPECL input clock. The 18 outputs are 2.5 V or 3.3 V LVCMOS compa

文件：69.12 Kbytes 页数：11 Pages

恩XP

Low voltage 1 : 10 CMOS clock driver 3-stateable outputs

General description The PCK946 is a low voltage CMOS 1 : 10 clock buffer. The 10 outputs can be configured into a standard fan-out buffer or into 1× and 1⁄2× combinations. The ten outputs were designed and optimized to drive 50 Ω series or parallel terminated transmission lines. With output-to-ou

文件：87.89 Kbytes 页数：13 Pages

恩XP

20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL

General description The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The devices employ a fully dif

文件：92.41 Kbytes 页数：15 Pages

恩XP

50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver

DESCRIPTION The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The devices employ a fully differentia

文件：71.1 Kbytes 页数：8 Pages

PHI

飞利浦

50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver

DESCRIPTION The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The devices employ a fully differentia

文件：71.1 Kbytes 页数：8 Pages

PHI

飞利浦

20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL

General description The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The devices employ a fully dif

文件：92.41 Kbytes 页数：15 Pages

恩XP