50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver

DESCRIPTION The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The devices employ a fully differentia

文件：71.1 Kbytes 页数：8 Pages

PHI

PHI

20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL

General description The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The devices employ a fully dif

文件：92.41 Kbytes 页数：15 Pages

恩XP

20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL

General description The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The devices employ a fully dif

文件：92.41 Kbytes 页数：15 Pages

恩XP

20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL

General description The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The devices employ a fully dif

文件：92.41 Kbytes 页数：15 Pages

恩XP