20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL

General description The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The devices employ a fully dif

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恩XP

Sales Outline Drawing

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MSPI

马洛里

50 AMP 300 - 500 VOLTS 35 nsec HYPER FAST RECTIFIER

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SSDI

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SSDI