CK00 100/133 MHz spread spectrum differential system clock generator

DESCRIPTION The PCK2022R is a clock synthesizer/driver for a Pentium III™ and other similar processors The PCK2022R has eight differential pair CPU current source outputs, one 33/66 MHz output which is configurable on power-up, two 48 MHz clocks which can be disabled on power-up, and one 3.3 V r

文件：102.32 Kbytes 页数：14 Pages

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CK408 66/100/133/200 MHz spread spectrum differential system clock generator

DESCRIPTION The PCK2023 is a clock synthesizer/driver for a Pentium IV and other similar processors. The PCK2023 has three differential pair CPU current source outputs. There are ten PCI clock outputs running at 33 MHz and two 48 MHz clocks. There are six 3V66 outputs. Finally, there is one 3.3

文件：177.86 Kbytes 页数：30 Pages

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PHI

CK408 66/100/133/200 MHz spread spectrum differential system clock generator

DESCRIPTION The PCK2023 is a clock synthesizer/driver for a Pentium IV and other similar processors. The PCK2023 has three differential pair CPU current source outputs. There are ten PCI clock outputs running at 33 MHz and two 48 MHz clocks. There are six 3V66 outputs. Finally, there is one 3.3

文件：177.86 Kbytes 页数：30 Pages

PHI

PHI

CK408 66/100/133/200 MHz spread spectrum differential system clock generator

DESCRIPTION The PCK2023 is a clock synthesizer/driver for a Pentium IV and other similar processors. The PCK2023 has three differential pair CPU current source outputs. There are ten PCI clock outputs running at 33 MHz and two 48 MHz clocks. There are six 3V66 outputs. Finally, there is one 3.3

文件：177.86 Kbytes 页数：30 Pages

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PHI

70 - 190 MHz I2C differential 1:10 clock driver

DESCRIPTION The PCK2057 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs and one differential pair of feedback clock outputs. The clock outputs are controlled by the clock inputs (C

文件：95.18 Kbytes 页数：12 Pages

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PHI

70 - 190 MHz I2C differential 1:10 clock driver

DESCRIPTION The PCK2057 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs and one differential pair of feedback clock outputs. The clock outputs are controlled by the clock inputs (C

文件：95.18 Kbytes 页数：12 Pages

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PHI

Low voltage dual 1-5 differential ECL/PECL clock driver

DESCRIPTION The PCK210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The input signals can be either differential or single-ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. The PCK210 is specifically designe

文件：93.44 Kbytes 页数：10 Pages

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PHI

Low voltage dual 1-5 differential ECL/PECL clock driver

DESCRIPTION The PCK210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The input signals can be either differential or single-ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. The PCK210 is specifically designe

文件：93.44 Kbytes 页数：10 Pages

PHI

PHI

Low voltage dual 1-5 differential ECL/PECL clock driver

DESCRIPTION The PCK210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The input signals can be either differential or single-ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. The PCK210 is specifically designe

文件：93.44 Kbytes 页数：10 Pages

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PHI

50-150 MHz 1:9 SDRAM clock driver

DESCRIPTION The PCK2509S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLLto precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The PC

文件：70.65 Kbytes 页数：10 Pages

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