PCK2057中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The PCK2057 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs and one differential pair of feedback clock outputs. The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the

2-line serial interface (SDA, SCL), and the analog power input (AVDD). The two-line serial interface (I2C) can put the individual output clock pairs in a high-impedance state. When AVDDis tied to GND, the PLL is turned off and bypassed for test purposes.

FEATURES

• Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications supporting DDR 200/266/300/333

• Full DDR solution provided when used with PCK2002P or PCK2002PL, and PCK2022RA

• 1-to-10 differential clock distribution

• Very low jitter (< 100 ps)

• Operation from 2.2 V to 2.7 V AVDD and 2.3 V to 2.7 V VDD

• SSTL_2 interface clock inputs and outputs

• HCSL to SSTL_2 input conversion

• Test mode enables buffers while disabling PLL

• Tolerant of Spread Spectrum input clock

• 3.3 V I2C support with 3.3 V VDDI2C

• 2.5 V I2C support with 2.5 V VDDI2C

• Form, fit, and function compatible with CDCV850